TSMC has begun mass production of its 2-nanometer chips, the company said, marking the next step in the race to shrink transistors for phones, servers, and AI accelerators. The Taiwanese foundry plans to ship 2nm wafers to customers through 2026, with four fabs coming online to support a combined target of 100,000 wafers per month.
The 2nm node, which TSMC brands N2, uses gate-all-around transistor architecture rather than the FinFET design that has dominated since 16nm. Compared with the 3nm generation, the company claims up to 15 percent better performance at the same power, or up to 30 percent lower power at the same performance. Those gains matter most for AI training chips and high-end mobile processors, where power budgets are tight and every watt counts.
The timing is the point. Apple and Nvidia are among the first customers expected to take volume in 2026, and TSMC's two initial 2nm plants are already reportedly sold out for the year. That means any company that did not lock in allocation early is now waiting for later capacity, which pushes the next wave of product launches into 2027.
By paragraph three the reader should already see the stakes: a single foundry controls the most advanced manufacturing on earth, and its 2026 output is spoken for. That concentration shapes product roadmaps, pricing, and even national industrial policy for the next two years.
Why 2nm Capacity Is Already Gone
TSMC's N2 fabs in Hsinchu and Kaohsiung are the first to reach volume, and industry reports put their combined monthly output at a level that fills quickly once Apple and Nvidia commit. The company has said it will have four 2nm plants running by 2026, but ramping a new node takes quarters, not weeks. Yields on a first-generation gate-all-around process are typically lower than on mature FinFET lines, so the effective supply of good dies is smaller than the headline wafer count suggests.
That scarcity has a price. Analysts expect 2nm wafers to cost roughly 30 percent more than 3nm wafers, which in turn raises the bill of materials for flagship phones and data-center accelerators. For Nvidia, which sells GPUs into a market with strong demand, the higher cost is absorbable. For phone makers competing on price in Southeast Asia and India, it is harder to pass through without cutting margins.
The cost also lands on consumers, though with a lag. A flagship phone built on 2nm silicon in late 2026 will carry a higher price than its 3nm predecessor, and mid-range devices will stay on older nodes longer. That extends the life of 3nm and even 4nm fabs, which is good news for the equipment makers who already sold the tools.
The Real Contest Is Samsung and Intel
Samsung Foundry has its own 2nm process, SF2, and has been courting the same customers. The company's track record on yield at leading nodes has been weaker than TSMC's, which is why several fabless designers kept their 2nm orders with TSMC despite Samsung's aggressive pricing. Still, a second viable source matters for customers who do not want single-supplier risk on their most expensive component.
Intel is the other contender, though on a different timeline. Intel 18A, its 1.8nm-class node, entered risk production in 2025 and is meant to support both internal products and external foundry customers. Intel has said it will make 18A available to outside designers, but attracting a tier-one customer like Apple or Nvidia would be the proof that its foundry strategy is working. So far, the public announcements have been internal.
The gap between a process node's announcement and its first high-volume customer is where foundry competition is actually decided. TSMC's advantage is not the headline number. It is the combination of yield, delivery record, and the ecosystem of packaging and design tools around the node.
Samsung's challenge is not technology alone. It is trust. A customer moving a flagship product to a new foundry risks a year of production if yields disappoint. That risk premium keeps TSMC's order book full even when a rival offers a lower price.
What It Means for the Rest of the Industry
For equipment makers, the 2nm ramp is business. ASML's extreme ultraviolet lithography machines are required at this node, and each new fab order is a multi-hundred-million-dollar line item. Applied Materials, Lam Research, and Tokyo Electron also benefit from the deposition and etch steps that gate-all-around transistors require. The capital spending wave is concentrated in Taiwan for now, but TSMC's Arizona and Japan fabs are slated to follow with 2nm or 3nm production later in the decade.
For governments, the concentration is the worry. The United States has spent years trying to onshore advanced chipmaking through the CHIPS Act, yet the most advanced node in volume production still sits in Taiwan. Export controls on semiconductor manufacturing equipment to China, tightened again in recent years, are meant to slow a rival's progress, but they also fragment the supply chain that every country depends on. It is not clear this will hold without more domestic capacity actually shipping.
China's response is to build around the restrictions. Domestic foundries are pushing mature nodes and investing in packaging and memory, where controls are looser. That does not close the gap at 2nm, but it does create a parallel supply chain for everything below the leading edge, which is where most of the world's chips actually are.
The Outlook for 2026 and Beyond
The next signal to watch is whether Samsung or Intel can claim a named 2nm-class customer in 2026. If they cannot, TSMC's lead widens from a technology gap into a structural one, and the pricing power that comes with sold-out fabs becomes harder to challenge. Customers will grumble, but they will keep paying, because the alternative is a delayed product.
TSMC's own roadmap does not stop at 2nm. The company has outlined A16, a 1.6nm-class node, for 2027, and has begun talking about angstrom-era processes beyond that. Each step demands more capital, more EUV machines, and more engineering talent, all of which are in short supply. The race is no longer just about who can print the smallest transistor. It is about who can finance and staff the next fab.
For more on the export-control side, see Reuters coverage of semiconductor policy.