TSMC brought its 2nm (N2) process into volume production in the fourth quarter of 2025, the company says on its own technology page, and the node is now ramping through 2026 with capacity that two of its local plants have already sold out for the year. The shift matters because N2 is the first TSMC node built on first-generation nanosheet transistors, a break from the FinFET architecture that carried 3nm and every node before it.
The company describes N2 as delivering full-node strides in performance, power efficiency, and logic density over 3nm, and it is aimed at smartphones and high-performance computing rather than mature-node commodity parts. Apple has reportedly secured more than half of the available 2nm capacity, according to Presenc AI's research on 2026 allocation, leaving AMD and other customers to compete for the remainder. That concentration is the story: a single foundry's newest node is being rationed before the first mass-market product ships.
Why this matters now is simpler than the marketing suggests. AI accelerators and flagship phone chips are the only products that can absorb a 2nm wafer cost, so the buyers fighting for capacity are the same companies setting the pace of the AI buildout. If TSMC cannot add 2nm lines faster than demand grows, the constraint moves downstream into server shipments and device launch calendars. It is not clear this will hold through 2027, when A16 and the second-generation nanosheet nodes arrive.
What N2 actually changes
N2's headline feature is the nanosheet transistor, sometimes called a gate-all-around design, where the channel is a thin sheet of silicon wrapped by the gate on all four sides. TSMC's page calls this its first-generation nanosheet technology and pairs it with full-node improvements in performance and power. The practical effect for chip designers is better electrostatic control at small geometries, which translates into lower leakage and higher drive current than FinFET at comparable dimensions.
The node also marks TSMC's last major step before it moves to backside power delivery. A16, the next node in the roadmap, integrates nanosheet transistors with a backside power rail that the company says brings greatly improved logic density and performance. Backside power moves the power delivery network to the back of the die, freeing front-side routing for signals. That is a real architectural change, not a marketing rename, but it also adds process steps and cost.
Who gets the wafers
Apple's reported share of more than 50 percent of 2nm capacity is the headline number, and it fits the company's pattern of buying first access to TSMC's newest nodes for iPhone and Mac chips. The remaining capacity is split among AMD, Qualcomm, and a handful of AI accelerator designers, according to the allocation research. Supply-chain reports from Taiwan through September and October 2026 pointed to an accelerating mass-production ramp, with AMD among the customers cited.
That allocation has consequences. A fabless company without a TSMC allocation at 2nm cannot simply move to Samsung or Intel Foundry on short notice, because porting a design between foundries takes quarters and sometimes years. The result is that 2nm access has become a competitive weapon rather than a commodity input, and smaller chip designers will stay on 3nm or 4nm longer than their roadmaps assumed.
The capacity problem
TSMC's 3nm and 2nm expansion is running in parallel, according to New Electronics, as the company steps up advanced manufacturing capacity on both fronts. Running two leading-edge ramps at once strains equipment supply, especially extreme ultraviolet lithography tools, and it is the reason lead times for EUV scanners have become a bottleneck conversation again. ASML's delivery schedule, not TSMC's ambition, is what sets the pace here.
The sold-out status at two plants for 2026 also means price pressure. Foundry pricing at the leading edge already reflects scarcity, and a fully booked 2nm line gives TSMC leverage in contract negotiations that 3nm pricing did not have two years ago. Customers will pay, because the alternative is shipping a slower chip, but the margin expansion shows up in TSMC's quarterly results rather than in anyone's product roadmap.
What comes after N2
The roadmap after N2 runs A16, then A14, with each step adding backside power and further nanosheet refinement. TSMC's own page lists A12 as a second-generation backside power rail solution for AI and HPC, which suggests the company is already tuning the platform for accelerator workloads rather than phone SoCs. That is a quiet admission that AI chips, not handsets, are the economic driver of the leading edge.
The Semiconductor Industry Association put global semiconductor sales at $517.7 billion in the third quarter of 2026, and Deloitte's 2026 outlook projects the industry reaching $975 billion for the full year, a historic peak fueled by AI demand. Those numbers are the context for why a sold-out 2nm line matters: the money is in AI, and AI needs the newest silicon.
The honest caveat
Node names are not what they used to be. A 2nm label describes a marketing-era density target more than a physical gate length, and comparing TSMC's N2 to Intel's 18A or Samsung's SF2 requires looking at actual transistor density and power figures rather than the number on the slide. Intel's 18A uses a similar nanosheet approach with backside power, and Samsung's SF2 is in its own ramp, so the competitive gap is narrower than the node names imply. TSMC still leads on yield and volume, but the technology lead is measured in quarters, not years.
Export controls add another variable. The U.S. rules that restrict advanced chip sales to China, updated most recently in October 2024, do not stop TSMC from selling 2nm wafers to Chinese customers directly, but they do limit where those chips can end up. That creates a compliance layer on top of allocation, and it is one more reason capacity planning at the leading edge has become a geopolitical exercise.
What to watch
The metric that matters is not the node name but the yield ramp. TSMC has not published N2 yield figures, and until it does, the effective capacity is lower than the headline plant count suggests. If yields climb on schedule, the 2026 sold-out status eases by late 2027 as A16 comes online. If they stall, the shortage deepens and AI accelerator roadmaps slip.
Apple's next iPhone and Mac generations will be the first public proof of N2 performance in the wild, and AMD's server parts will follow. Those launches, not press releases, are how the industry will judge whether the 2nm transition paid off. Watch the benchmarks when they arrive.
For broader context on the foundry landscape, see Reuters semiconductor coverage and our own semiconductor desk.
