TSMC's 3nm capacity is fully allocated for the next 18 to 24 months, leaving no room for new orders through 2027. The foundry's N3 and N3E lines run at utilization rates near 100 percent, driven by demand for AI accelerators from a handful of hyperscale customers who have booked capacity years in advance. This tight allocation is not a temporary blip; it is a structural response to sustained demand growth that has outpaced any planned expansion through 2028.
A 3nm wafer now costs about $19,500, with prices ranging from $17,000 to $22,000 depending on volume and contract terms. Lead times for N3 capacity exceed 50 weeks, and TSMC has signaled pricing will rise 3 to 5 percent for 2026 orders. The constraint is not just silicon. Advanced packaging, the step that turns wafers into usable chips, is tighter still. Without enough advanced packaging capacity, even a wafer is useless; it cannot be assembled into a working accelerator for AI training or inference.
CoWoS-L packaging capacity is fully booked through 2026, with lead times of 40 to 52 weeks. Demand for the packaging format used in large multi-die designs like NVIDIA's B200 outpaces the expansion ramp, and CoWoS demand overall exceeds supply by 40 to 50 percent. TSMC's CoWoS-S 2.5D packaging costs about $70 per unit, while terão stacking through SoIC runs about $120 per unit. Intel's EMIB alternative costs roughly $35 per unit. For customers focused on cost, EMIB offers a cheaper path, but it cannot handle the die count needed for the largest AI accelerators.
HBM Prices Jump 20 Percent as Memory Becomes the Real Bottleneck
HBM3e contract pricing rose about 20 percent quarter over quarter as SK Hynix, Samsung and Micron allocate 2026 capacity against booked AI accelerator demand. With HBM now the largest single line in modern accelerator bills of materials, that increase flows straight into device cost. Micron reported record data center gross margin and said DRAM and NAND demand significantly exceeds supply through calendar 2027.
Hyperscalers are treating memory access as a structural bottleneck, not a cyclical squeeze. About $22 billion in customer prepayments have been committed to lock in memory supply. SK Hynix has begun HBM4 sampling to its lead AI accelerator customer ahead of schedule, reinforcing its position into the next memory generation. Samsung also announced plans to expand its HBM production lines, but those expansions will not be online until 2027 at the earliest.
The memory squeeze matters because it shifts where cost accumulates. Logic foundry pricing gets the headlines, but memory and packaging now determine how many chips ship and at what margin. A hyperscaler that secures HBM supply early can build more accelerators at lower cost than a competitor who waits. That dynamic is why prepayments have become a competitive weapon rather than a routine procurement step. The data center economics now favor those who can lock in memory supply early, creating a new tier of competitive advantage based on memory access.
Why the Constraint Will Not Ease Quickly
TSMC has confirmed it will add another 3nm fab in Tainan, with production starting in the first half of 2028. That is not soon enough to relieve 2026 or 2027 pressure. The company held mult annual capital expenditure at $60 to $64 billion, a level that signals expansion without a capacity surge. New fabs take years to equip and qualify, and advanced packaging lines take longer than wafer fabs because the equipment base is narrower.
Foundry utilization at mature nodes tells a different story. While leading edge runs near 100 percent, some mature node foundries operate at 70 to 80 percent capacity. That split shows where the money flows. AI demand concentrates on the most expensive nodes and packaging formats, leaving older processes with slack. Customers on mature nodes still have negotiating room, but anyone needing 3nm or below does not. The cost premium for advanced nodes is now justified only if you can also get the advanced packaging and memory that make those designs viable.
It is not clear the constraint will hold through 2028. TSMC's Tainan expansion and competing capacity from Intel and Samsung could ease supply if AI demand growth slows. But the HBM deficit, with Micron projecting it extends beyond 2027, suggests memory rather than logic will remain the binding limit. The two problems move on different timelines, which makes planning harder. The memory issue has a longer tail, which means the overall chip shortage will persist beyond the point where logic capacity begins to rise.
What This Means for Chip Buyers
Buyers planning 2026 and 2027 product cycles face a simple problem. They cannot buy their way out of the shortage at current prices, and waiting carries its own cost. Lead times of 50 weeks for wafers and 40 to 52 weeks for CoWoS packaging mean design decisions made today lock in supply for late 2026 at best. The window for planning and production is now too tight for traditional lead times, and it forces buyers into a shorter decision cycle.
The practical response is to diversify. Some customers are qualifying Intel EMIB at $35 per unit for cost sensitive designs, or shifting portions of work to Samsung's foundry. Others are redesigning to reduce HBM content per accelerator. None of these moves is fast, and all carry qualification risk. For smaller chip designers without hyperscale budgets, the squeeze is felt most acutely, since they lack the leverage to secure priority allocation. The competitive landscape now favors those with deep pockets who can lock in multiple supply channels years in advance.
The market data points to one conclusion. AI chip supply in 2026 is constrained at three points simultaneously: logic wafers, HBM memory, and advanced packaging. Fixing one does not fix the others. Until the Tainan fab ramps in 2028 and HBM capacity expands past 2027, the bottleneck stays structural. The longer term picture includes HBM4 sampling by SK Hynix, but that is still years away from volume production. Intel's EMIB alternative could provide some relief for smaller designs, but the largest AI accelerators will remain dependent on TSMC's CoWoS and HBM supply.
Readers tracking this space can follow related coverage in the Semiconductors category. For more on how foundry pricing and packaging costs feed into accelerator economics, see the Semiconductor Market Data dashboard.
Customers who locked supply early will ship more product at lower cost through 2027, and everyone else will wait.