TSMC reported first-quarter 2026 revenue of $35.9 billion, a 66.2% gross margin, and raised its full-year growth forecast above 30%. The headline numbers are strong. The more telling detail is what the company said about capacity: its most advanced nodes are already sold out well into 2026, and the 2nm ramp is tightening faster than analysts expected.
The company's 3nm monthly capacity in Taiwan is expected to exceed 200,000 wafers by the end of 2026. That figure matters because 3nm is the node where Apple, Nvidia, AMD, and Qualcomm all compete for allocation. Fab 18B, the main 3nm production base, runs between 140,000 and 160,000 wafers per month today. Utilization is high enough that TSMC has broken its usual practice of keeping spare capacity on advanced nodes.
This is the nut graf: the constraint is not demand. Demand is visible and booked. The constraint is physical fab space, and it is biting now, in 2026, not in some distant future. Every major chip designer is paying a premium for access, and the companies without locked-in allocation are the ones watching their product roadmaps slip.
What TSMC Actually Said
TSMC does not usually talk in dramatic terms. On the earnings call, management framed the situation as a capacity-rule break, a phrase that caught analysts' attention because TSMC's entire model rests on predictable capacity planning. Breaking that rule means the company is accepting orders it cannot fully serve with existing tools, which in turn means new fabs are being pulled forward.
The company has not broken this rule before in a way visible to outsiders. Past capacity crunches were managed by reallocating tools between nodes, a trick that works when demand is uneven. This time, demand is even across 3nm and 2nm, so reallocation only moves the shortage around. That is why the rule had to break.
The 2nm process is in short supply before it has even reached volume. TSMC has seven fabs in Taiwan working on advanced nodes, and the 2nm line is already overbooked by customers who need it for next-generation mobile and AI accelerators. The company is reportedly planning 12 new advanced process and packaging fabs in Taiwan to relieve the pressure.
TrendForce reported that 3nm capacity has become so tight that further expansion is required, while 2nm is also in short supply. That is two consecutive generations of leading-edge silicon running hot at the same time, which has not happened since the early FinFET era.
The AI Demand Layer
The driver is not only smartphones. AI accelerators are consuming an outsized share of advanced-node capacity, and the orders are large and long-dated. Nvidia and AMD both need leading-edge silicon for their next-generation accelerators, and both have signaled that they will take whatever allocation TSMC can offer.
This creates a squeeze on everyone else. A mobile chip designer that needs 3nm in the second half of 2026 is now competing for the same wafers as an AI accelerator customer with a larger contract. The result is a queue, and the queue is rationed by relationship and volume, not by price alone.
It is not clear this will hold. TSMC's gross margin of 66.2% assumes pricing power that depends on no competitor catching up. Samsung's foundry business is still trying, and Intel Foundry is still trying. If either ships a credible alternative at 2nm or below in 2027, TSMC's pricing leverage narrows.
Fab Construction and the Real Bottleneck
Building a fab is slow. TSMC is expanding at several sites, including Fab 25 in Taichung, which is being developed for A14, a 1.4nm-class process, later in the decade. Fab construction timelines run three to five years from groundbreaking to first wafers, which means decisions made in 2026 determine supply in 2029.
The global fab construction picture is busy but uneven. Some regions are adding capacity faster than others, and the advanced-node concentration remains in Taiwan. That concentration is the single biggest structural risk in the semiconductor supply chain, and it is not being solved by 2026 construction plans.
Equipment is the other bottleneck. EUV lithography tools from ASML are the gating item for every advanced node, and delivery slots are booked years ahead. A fab without EUV tools is a building, not a factory.
What This Means for Customers
Chip designers are responding in three ways. First, they are locking in multi-year supply agreements, paying premiums for guaranteed allocation. Second, they are accelerating design work on older nodes where capacity is more available, trading performance for certainty. Third, they are diversifying, qualifying second sources at Samsung or Intel even when those sources are not the best option.
The second strategy is the one most consumers will notice. Products that would have used a 3nm chip are shipping on 4nm or 5nm instead, with the performance difference papered over in marketing. The gap is real but small for most use cases, and the cost savings are real.
The third strategy is slower and riskier. Qualifying a new foundry takes 18 to 24 months, and the yield curves at a new node are steep. Most customers will not see meaningful diversification before 2027.
The Outlook
TSMC's raised guidance above 30% growth for 2026 implies confidence that the capacity it has will be sold at premium prices. That is a bet that demand stays strong and that competitors do not close the gap. Both could go wrong, but neither looks likely in the near term.
The more interesting question is whether the 2nm shortage resolves by 2027 or persists into 2028. If TSMC's 12 new fabs come online on schedule and EUV deliveries hold, supply catches up. If any of those slips, the shortage becomes the defining constraint of the AI hardware cycle, and every chip designer's product plan becomes a negotiation.
The next earnings call will be watched for one number: the 2nm capacity figure for 2027. Until then, the industry's planning horizon is shorter than its product roadmap, and that gap is where the money is made or lost.
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According to Reuters, TSMC's expansion plans continue to draw close attention from customers and competitors alike.
