TSMC started volume production of its N2 process node in late 2025, and by early 2026 most of that capacity is already spoken for. Apple, Nvidia, Qualcomm, and AMD have reportedly locked in large shares of the initial output, leaving latecomers to hunt for wafer slots at Intel, Samsung, or Rapidus. The crunch is not a blip. It is the shape of the 2nm era.
The N2 node promises up to 15% higher performance or substantial power reductions over the previous generation, which is why AI accelerator makers want it badly. Those chips eat more wafer area per device than a mobile processor does, so a single AI order consumes capacity that used to feed dozens of phone chips. That math is what turned a tight market into a sold-out one.
TSMC is spending to fix it. Capital expenditure ran $29.8 billion in 2024, $40.9 billion in 2025, a 37% jump, and a planned $52 to $56 billion in 2026. Monthly wafer starts across Hsinchu Baoshan, Kaohsiung, and other sites are targeted well into six figures by 2026 to 2028. Whether that money buys enough capacity depends on yields, which TSMC has not disclosed for N2 but which industry watchers describe as strong enough to justify the ramp.
The stakes, plainly: if you are designing a chip that needs 2nm-class silicon in 2026, your foundry choices are limited and expensive, and your launch date depends on a slot you probably should have booked last year. That matters for phone makers, AI labs, and the car and defense suppliers further down the queue.
Why TSMC Still Owns the Leading Edge
Intel wants to be the alternative. Its 18A node, roughly in the same generational tier, entered production in 2025 with Panther Lake as the first major product, and it carries two tricks TSMC does not yet ship at scale: RibbonFET gate-all-around transistors and PowerVia backside power delivery. Intel was first to both in production. The problem is the foundry business around them. External customer adoption is still small next to TSMC's global base, and 18A yields, while improved through mid-2025, sit behind N2. Lip-Bu Tan, Intel's CEO, has talked up wafer agreements from top semiconductor companies, but talk is not booked capacity.
Samsung is the third option and the weakest of the three right now. Its SF2 node targets mass production in 2026, with the Taylor, Texas fab carrying much of the load. Samsung offers competitive pricing and was early to gate-all-around transistors, but yield stability has kept customers cautious. Trust runs on predictable yield in this business, and Samsung has not yet earned enough of it at 2nm to win high-volume orders away from TSMC.
Intel and Samsung Chase the Same Customers
Rapidus is the wildcard. The Japan-backed foundry raised another $1.7 billion, bringing its combined government and private funding to $11.3 billion, against an estimated $32 billion needed for full-scale 2nm production by 2027. That gap is real. Rapidus is not trying to out-volume TSMC. It is pitching short turnaround times and tailored service to custom chip designers and domestic Japanese firms who need smaller lots. If it hits its 2027 target, it adds a fourth source, but only a niche one.
The broader picture is a capacity tightrope. Demand from AI, high-performance computing, and flagship mobile devices keeps outrunning supply at the top nodes, and the number of companies that can actually build at 2nm is four, one of which is not yet shipping. Securing wafer slots early has become mission-critical for the biggest tech companies and a hard wall for everyone else. Reuters has tracked the foundry race closely, and the pattern is consistent: whoever owns the leading edge owns the pricing power.
It is not clear this will ease by 2027. TSMC's capex trajectory says the company expects demand to stay hot, and the AI accelerator trend of larger die sizes is not reversing. Intel and Samsung have a window to prove they can deliver, but windows close. If 18A and SF2 yields do not converge with N2 soon, the 2nm market stays a one-horse race for another node cycle, and the supply crunch becomes a structural feature rather than a temporary squeeze. You can follow our semiconductors coverage for updates as these fabs ramp.
Rapidus and the Fourth Foundry Question
Rapidus plans to begin 2nm-class production around 2027 and ramp monthly output within a year of launch. Whether $11.3 billion gets it there, or whether it needs the full $32 billion first, is the open question for Japan's chip ambitions and for anyone hoping for a fourth foundry option. The answer will shape whether 2nm stays a seller's market or finally gets competitive pricing.
TSMC's N2 capacity being sold out through 2026 also has knock-on effects for the rest of the supply chain. Equipment makers, materials suppliers, and packaging houses all see demand pull from the same fabs, which strains their own capacity. Advanced packaging in particular has become its own bottleneck, with co-packaged optics and chiplet integration adding steps that compete for the same tool time. The foundry crunch is not just a wafer story.
For chip buyers, the practical advice is blunt. Book early, qualify a second source, and expect to pay premium pricing for 2nm-class silicon through at least 2027. The days of treating foundry capacity as a commodity are over, at least at the leading edge, and the companies that internalized that lesson early are the ones shipping products on schedule. The capacity crunch is not a temporary squeeze. It is the new baseline for anyone building at the leading edge.
There is also a geopolitical layer that makes the crunch harder to solve. Most of TSMC's leading-edge capacity sits in Taiwan, which concentrates risk for every company that depends on it. Intel's Arizona fabs and Samsung's Taylor plant are partly a hedge against that concentration, and government subsidies in the United States, Japan, and Europe are explicitly designed to spread advanced manufacturing across more locations. Those fabs will take years to reach volume, and even then they will not match Taiwan's density of talent and supplier networks. The diversification effort is real, but it is a decade-long project, not a quick fix for 2026.
Memory makers face a parallel squeeze. High-bandwidth memory for AI accelerators is itself capacity-constrained, and the same foundries that print logic also package the stacks that sit beside it. When wafer slots are scarce, HBM supply tightens too, which feeds back into accelerator pricing. The 2nm crunch is not an isolated event. It ripples through every layer of the stack that AI depends on.