TSMC is reportedly planning a major expansion of its 2nm and 3nm advanced process capacity to meet surging demand for artificial intelligence and high-performance computing chips. Supply chain sources indicate the company aims to boost 2nm monthly capacity to 110,000 wafers by mid-2027, up approximately 22% from 90,000 wafers at the end of 2026.
The 3nm monthly capacity is set to rise from 180,000 to 210,000 wafers over the same period, a gain of more than 16%. Measured against the 120,000 to 130,000 wafers at the end of 2025, that would represent a capacity increase of nearly 70% within 18 months.
The expansion matters right now because AI-related demand visibility at TSMC extends to 2029-2030, according to statements the company made at its second-quarter earnings call in July. With 2nm volume production ramping and 3nm remaining a primary shipment driver in the near term, the capacity race is becoming a binding constraint on how fast AI accelerators reach the market.
Capacity Targets and Timeline
TSMC has for the first time communicated its 2027 expansion plans to partner suppliers, according to the latest supply chain information. The 2nm target of 110,000 wafers per month by mid-2027 compares with 90,000 wafers at the end of 2026, while 3nm moves from 180,000 to 210,000 wafers over the same window.
The 3nm trajectory is the more striking of the two. With 120,000 to 130,000 wafers per month at the end of 2025, reaching 210,000 by mid-2027 would be a near-70% increase in 18 months. Analysts note that this reflects how, even as 2nm enters volume production, 3nm remains one of the main shipment drivers in the near term, with market demand still exceptionally strong.
The N2 family, featuring nanosheet architecture and backside power rail design, is expected to begin contributing revenue in the second quarter of 2026. The A16 process, which incorporates Super Power Rail technology, is slated for volume production in the second half of 2026. The A14 process, TSMC's second-generation angstrom-class node, is progressing smoothly with production bases in Taichung and Hsinchu, targeting volume production in the third quarter of 2028, with plans to advance to the A10 node around 2030.
Three-Region Expansion
To fill the substantial advanced process capacity gap, TSMC is simultaneously initiating 3nm production line construction and conversion across Taiwan, the United States, and Japan. Market sources indicate the company plans to add new fab buildings at the Tainan Science Park, while its second fab in Arizona and second fab in Japan will also incorporate 3nm technology.
3nm production at the Arizona fab is targeted to commence in the second half of 2027. If progress stays on track, the volume production timeline could be pulled ahead of the original schedule. Beyond new fab construction, TSMC is also flexibly converting some 5nm equipment at its Taiwan facilities to 3nm capacity, a shift analysts link to weakening demand for entry-level and mid-range smartphones and for mature process nodes.
TSMC currently has 18 fabs under construction or renovation worldwide, with the pace of expansion growing exponentially. It is not clear this pace can be sustained without supply chain friction, particularly for equipment and skilled labor in new regions, but the company has the order visibility to justify the bet.
Capital Spending and Advanced Packaging
TSMC has substantially raised its 2026 capital expenditure to $60-64 billion, a significant upward revision from the original $50 billion range. Approximately 70% to 80% of that will be allocated to N3 and N2 advanced process capacity expansion.
The AI wave continues to drive advanced packaging demand. CoWoS monthly capacity could double from approximately 130,000 wafers at the end of 2026 to 260,000 wafers by the end of 2028, with expansion focused on the Zhunan AP7 facility in Taiwan and the Arizona fab. CoWoS has become an indispensable supply chain link for AI chip giants such as Nvidia.
Analysts forecast 2026 USD revenue growth of over 40%, with 2026 post-tax earnings per share projected at NT$106.46, potentially rising to NT$139.47 in 2027. Domestic institutional investors maintain a Buy rating with a target price of NT$3,200, according to the Reuters report on the company's outlook.
Competitors and the Packaging Landscape
Intel's positioning in the advanced packaging arena is also drawing market attention. Analysts estimate that Intel's EMIB-T packaging capacity, measured in 12-inch CoWoS-equivalent wafers, could climb from 15,000 to 20,000 wafers per month in 2027 to 40,000 to 45,000 wafers in 2028. Industry sources note that the architecture is particularly well-suited to the custom AI accelerator requirements of Google and Amazon.
MediaTek has reportedly given Intel's EMIB packaging technology a "very good" assessment, indicating that yields are steadily improving and adding fuel to market speculation that Google may adopt EMIB for its TPU chip production. Nevertheless, TSMC's leadership in advanced packaging remains difficult to challenge in the near term.
TSMC has maintained its customary stance of not commenting on market speculation, emphasizing that all capacity-related disclosures are subject to official company announcements. Judging from the expansion notifications received by supply chain partners and the significant upward revision in capital expenditure, the company clearly holds a high degree of confidence in the medium- to long-term demand outlook for advanced processes.
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The expansion leaves TSMC's competitors chasing capacity that may not materialize until 2028, while Nvidia and other AI chip designers now have a clearer line of sight on wafer supply through 2027. Whether Intel can convert its EMIB momentum into real volume by 2028 is the question that will define the next phase of the advanced packaging market.
One more data point worth noting: the 2nm process entered volume production in 2026, so no capacity data exists for end-2025. That gap in the record is itself a sign of how quickly the node moved from roadmap to revenue, and it explains why the mid-2027 targets are being set so far ahead of current output.
For chip designers planning product roadmaps, the practical takeaway is simple: capacity at the leading edge is expanding, but it is being allocated years in advance, which favors customers with the deepest pockets and the longest planning horizons.