TSMC Develops 'EMIB Like' Packaging to Challenge Intel's Hold on Advanced AI Chip Assembly
TSMC is quietly building a packaging technology that mirrors Intel's Embedded Multi-die Interconnect Bridge, or EMIB, and it has recruited Taiwan's Kinsus Interconnect Technology to help. The Information reported the project on Thursday, citing people familiar with the matter, and the news jolted both companies' shares. Intel stock climbed about 12 percent on the day, while TSMC gained nearly 7 percent, according to GuruFocus via Yahoo Finance.
The move puts TSMC on a collision course with Intel Foundry in a corner of the chip business that has quietly become one of the most contested in the industry. Advanced packaging — the step where multiple silicon dies are wired together into a finished accelerator — is now the bottleneck that decides how many AI processors can ship. The lithography machines that print the transistors no longer set the pace by themselves.
Why packaging became the battleground
For years the industry assumed the next great chip war would be fought over process nodes — who can print the smallest transistors. That fight is still on. But as AI workloads grew, the real constraint moved to the back end of manufacturing. TSMC's CoWoS, short for Chip-on-Wafer-on-Substrate, stacks compute dies beside high-bandwidth memory on a silicon interposer, and demand for it has outraced supply for three straight years.
The squeeze is not new. In the middle of 2023, TSMC told analysts it had no problem supporting logic die demand on the front end, but admitted the back end — "especially the CoWoS" — was very hard to fill at 100 percent. By late 2024, after more than doubling capacity, executives said customer demand far exceeded the company's ability to supply. The gap has not closed since.
The numbers show how lopsided the market has become. TSMC held roughly 73 percent of pure foundry revenue in the first quarter of 2026, according to Counterpoint Research figures cited by the I/O Fund. Epoch AI estimates that Nvidia, Google, AMD, and Amazon together consumed more than 90 percent of CoWoS capacity in 2025. Goldman Sachs expects TSMC's CoWoS capacity to grow from about 675,000 wafers a month in 2025 to 1.275 million in 2026 and 2.31 million in 2027 — a tripling in three years that still may not satisfy demand. Some buyers now face 52- to 78-week lead times for finished packages, and Nvidia alone is said to book more than half of available CoWoS output.
That crunch is the opening Intel has been pointing at. EMIB embeds small silicon bridges inside the substrate to connect adjacent dies, avoiding the giant interposer that CoWoS depends on. Intel argues the approach lets chips grow larger and more complex while cutting cost and improving electrical efficiency. It sits at the center of Intel's Xeon roadmap, powers its Agilex FPGAs and the Ponte Vecchio data center GPU, and anchors the packaging pitch Intel Foundry makes to outside customers.
TSMC's answer to Intel's bridge
The project described by The Information, code-named "EMIB Like" inside TSMC, is an attempt to match that capability without licensing it. Kinsus, a Taiwanese substrate maker with deep roots in the packaging supply chain, is the partner on the work. Neither TSMC, Intel, nor Nvidia responded to requests for comment when Benzinga asked.
The report also revealed that Nvidia is evaluating Intel's EMIB for a future processor. That is a striking detail on its own. Nvidia is TSMC's biggest advanced-packaging customer, and its flagship accelerators are built on CoWoS. If Nvidia hedges part of its roadmap onto Intel packaging, the competitive stakes shift from the foundry floor to the negotiating table — and Intel would suddenly hold a card it has not held in years.
TSMC has not confirmed any of it. But the direction of travel is visible in its public roadmap. The company is standardizing its next packaging step, called Chip-on-Panel-on-Substrate, or CoPoS, on a 310 by 310 millimeter panel format. TrendForce expects 2026 to be a validation year for equipment and materials suppliers, pilot production in 2027, and mass production in the second half of 2028. Beyond CoPoS, TrendForce says, TSMC's next major focus is glass core substrates, with commercial-scale output likely after 2030.
Glass substrates enter the race
Intel fired its own shot in the same arena last week. The company announced a strategic collaboration with China's Lens Technology to accelerate glass substrate-based packaging, pairing Intel's packaging expertise with Lens's precision glass processing, as detailed in the Intel newsroom. Intel CEO Lip-Bu Tan called advanced packaging a critical factor as AI systems push performance, scale, and efficiency. Lens founder and chairwoman June Chau pointed to her company's work in glass materials, laser processing, and large-scale production. Institutional investors cited by Central News Agency expect mass production of glass core substrate packaging from that partnership as early as the second half of 2027.
Glass is attractive because it offers better dimensional stability, higher interconnect density, and lower power loss than the organic substrates used today. It also reshuffles the supplier map. China's BOE has moved into glass substrates too, spinning up a pilot line in 2024 and a fully automated line in the first half of 2026, with mass production eyed for 2028. Taiwan's panel makers are pushing back: Innolux and AUO are developing fan-out panel-level packaging on square glass panels, Innolux is working on glass through-via technology, and TPK-KY has invested in a pilot line of its own.
The OSAT layer is moving as well. Powertech, the Taiwanese packaging house, said during its second-quarter earnings call that it had joined AMD's AI chip supply chain and aims to be the first OSAT to mass-produce fan-out panel-level packaging for AI applications by mid-2027. It has also teamed with Broadcom on a joint venture in Singapore to develop additive fine-line redistribution layer technology for advanced packaging substrates.
What the packaging war means
None of this is theoretical posturing. Packaging capacity is now a line item in AI infrastructure planning, and the companies that control it control the pace of the AI buildout. TSMC's answer to EMIB matters because it threatens the one part of Intel's foundry story that had no real rival. If TSMC ships an EMIB-class technology, Intel's pitch to external customers — come for the packaging, not just the process — loses its edge. If Nvidia actually adopts EMIB, TSMC faces something it has rarely seen: a marquee customer with a credible alternative.
The stakes show up in the stock moves. A single report, unconfirmed by any of the three companies, was enough to lift Intel 12 percent and TSMC 7 percent. Investors are pricing the packaging war as a genuine fork in the road for both businesses.
The foundry economics behind it are stark. Intel Foundry booked $5.8 billion in revenue in the second quarter of 2026, but only $293 million of that came from external customers. TSMC took in $40.2 billion in the same quarter — roughly 137 times more. Advanced packaging is one of the few levers Intel can pull that does not depend on winning a process-node shootout it has been losing for a decade. EMIB, and now the glass substrate work with Lens, are the credible pieces of that story. TSMC's "EMIB Like" project is a direct answer to both.
Expect the next few months to bring more detail: whether TSMC confirms the project, whether Kinsus's substrate lines can scale, and whether Nvidia's evaluation turns into a contract. The Information's report is the opening bid, not the final word. For a sector that spent a decade arguing about nanometers, the argument has moved to millimeters of substrate and the bridges that connect them — and both Taiwan's foundry giant and America's chip veteran are placing their bets.
More on the broader chip industry in our Semiconductors section, including recent coverage of AI chip supply and memory.