CNBC reported on September 8 that TSMC and Samsung plan to use ASML's newest High-NA extreme-ultraviolet (EUV) lithography systems for advanced chip production. The two foundries are preparing for a period when AI accelerators need denser logic and faster memory, while chipmakers face tighter export rules and a supply chain that must serve several national markets at once. Each High-NA EUV scanner is reported to cost about $400 million, so the decision is both a technology bet and a major capital commitment.
Why High-NA EUV Matters for AI
Lithography is the process that draws circuit patterns onto silicon. Current EUV systems use light with a wavelength of 13.5 nanometers, but High-NA EUV uses optics with a larger numerical aperture, giving manufacturers more control over tiny features. ASML describes the approach as a major step in patterning technology because the larger aperture can fit more circuit detail into the same exposed area. For a foundry, that means designers can place more transistors on a die, shorten interconnect distances, or reduce the power needed for a given amount of computation.
AI accelerators put unusual pressure on that calculation. A modern accelerator is not a single block of logic. It combines compute units, cache, high-bandwidth memory interfaces, networking blocks, and safety or control circuitry. The package must move data quickly while keeping heat and latency under control. Smaller transistor features can improve performance, but the surrounding wiring and memory access often matter just as much. High-NA EUV gives foundries another way to improve the density of the silicon layers that connect these blocks.
TSMC is expected to use the technology for its next generation of advanced logic, with CNBC reporting that adoption is aimed for around 2030. Samsung's plan is more focused on memory first: the report says the company expects to use High-NA EUV for DRAM manufacturing beginning in 2028. That difference matters because memory and logic have different design rules, and the first production runs will reveal which parts of the process are ready for volume manufacturing.
Export Controls and Supply-Chain Pressure
The equipment decision arrives as governments continue to narrow the routes through which advanced semiconductor technology can move across borders. In June, U.S. lawmakers urged the administration to tighten rules for contract chipmakers that supply Chinese firms. Their request focused on the possibility that advanced manufacturing know-how could pass through a foundry before reaching a customer outside the United States. The proposal does not change the fact that ASML is a Dutch company, but it does increase pressure on foundries to document equipment use, customer relationships, and production destinations.
That scrutiny changes how a fab makes a capital plan. A $400 million scanner is not just a machine on a cleanroom floor. It is a long-term asset tied to a process node, a customer base, a service contract, and a set of export permissions. If a tool cannot be used for certain products or destinations, the financial return becomes harder to model. Foundries therefore need to balance customer demand with compliance requirements and the risk that a rule change could leave expensive equipment underused.
TSMC's expansion in Arizona adds another layer to that calculation. The company plans three fabs there, with production aimed at advanced 2 nm and 3 nm processes as demand develops. A High-NA tool installed in Taiwan serves one manufacturing system. A tool installed in Arizona supports a different customer mix, a different power grid, a different workforce, and a different regulatory environment. The equipment may be technically identical, but its role in the company's global network is not.
The Netherlands remains central to the supply chain because ASML is the only supplier of High-NA EUV systems. That concentration gives the toolmaker substantial influence over the pace of industry progress. It also gives governments a clear point of attention when they discuss export controls. The result is a supply chain in which the most advanced chips depend on a small number of suppliers for equipment, specialized materials, design software, and final assembly.
Impact on Memory and Logic Segments
Samsung's planned early use for DRAM could have a direct effect on AI servers. High-bandwidth memory is a major part of an accelerator system because the compute dies need a fast path to large pools of data. As neural-network models grow, designers must move more weights, activations, and intermediate results between memory and processing units. A memory process that improves density or bandwidth can reduce the distance data travels and can help a server deliver more useful work for each watt of electricity.
DRAM production is not as simple as shrinking a transistor array. The process must maintain uniformity across large wafers, control the shape of tiny capacitor structures, and keep defects from turning into failed chips. High-NA EUV can help with some of those patterns, especially where a tighter feature pitch allows more storage per unit area. Samsung has built a large memory business around process scale and yield, so its first High-NA run will be watched closely by customers that build AI accelerators.
TSMC's logic customers are likely to benefit in a different way. Nvidia, AMD, and other designers use foundry processes to combine many specialized blocks into one package. Finer patterning can support smaller standard cells, more routing layers, and tighter connections between compute and memory interfaces. The result may be a chip that delivers more performance at a lower voltage, although the exact gain depends on the design and the packaging chosen by the customer.
Foundry customers will also judge the technology by yield, not by a laboratory demonstration. A new scanner can produce promising test structures and still take years to become reliable at volume. Foundries must run thousands of wafers through the same process, measure variation across each wafer, and repair problems before a customer accepts the node. That is why the reported 2030 timing for TSMC is more useful than a single announcement: it places the equipment inside a multi-year development plan.
Advanced Packaging Integration
The value of High-NA EUV will depend on how well it works with advanced packaging. AI chips increasingly use chiplets, in which separate logic and memory dies are joined on an interposer or substrate. This approach lets designers combine components made on different processes, but it also creates a new set of routing and thermal challenges. A wide, reliable connection between logic and HBM can matter as much as the transistor count on the compute die.
CoWoS, or Chip on Wafer on Substrate, is one widely used packaging method. It places dies on a silicon interposer and connects that interposer to a larger substrate. As the number of connections grows, manufacturers need finer routing and more precise alignment. High-NA patterning can support smaller features on the silicon layers, while the packaging process must control warpage, solder joints, and heat flow. The two technologies are therefore part of the same production chain.
This connection is especially relevant for AI systems that use multiple accelerators in a server. A single chip may not contain all the memory or networking required by a large model. Designers can instead join several chiplets into a package that behaves like a larger system. The approach gives engineers flexibility, but it also makes the quality of the interconnect more visible to the final customer. A small defect or timing error can reduce the output of an entire server.
Foundries that master both front-end lithography and back-end packaging will have an advantage when customers ask for custom AI hardware. The customer can then choose the process node, the memory technology, and the package together rather than trying to fit separate parts into an awkward design. That level of coordination is likely to become a selling point as AI models move beyond the first generation of accelerator designs.
Broader Industry Outlook
The purchase of High-NA EUV systems shows how far semiconductor investment has moved from simple capacity expansion to process control at the edge of physics. A modern fab must manage light, mirrors, resist materials, contamination, and electrical measurement at the same time. The price of a scanner reflects that complexity, and the lead time for the equipment means that today's order can shape production more than a decade later.
TSMC and Samsung are making those commitments at a moment when AI demand remains strong but uncertain. Cloud providers want faster training and inference, automakers want chips that can operate under strict power limits, and governments want domestic access to advanced manufacturing. Those goals can pull the industry in different directions. High-NA EUV gives foundries a tool for meeting the most demanding designs, while export controls and regional factories push them to divide that tool across several markets.
The immediate effect will be seen in development schedules rather than in a sudden change to retail products. Customers need time to move designs to a new node, qualify packaging, and build enough supply to support commercial systems. Still, the decision is a clear signal that the industry does not expect AI chip complexity to slow down. TSMC, Samsung, and their customers are preparing for a generation of processors in which density, memory bandwidth, and packaging quality matter together.
For buyers of servers and devices, the practical benefit will be measured in performance per watt, availability, and price. A smaller transistor can help, but only if the complete system remains reliable. For the semiconductor industry, the larger lesson is that the next advance will not belong to a company that controls one step alone. It will belong to the teams that can connect design, lithography, memory, packaging, compliance, and manufacturing into one dependable flow.