TSMC A16 Nears Mass Production as Samsung Delays 1.4nm and Intel Targets 2028 for 14A
Supply Chain Reports Signal Q4 Launch for TSMC's 1.6nm Node with Backside Power Delivery
Taiwan Semiconductor Manufacturing Company has completed development and validation of its 1.6-nanometer-class A16 process node and is targeting the start of mass production in the fourth quarter of 2026, according to the latest supply chain reports. The timeline aligns with TSMC's prior guidance that A16 would enter production in the second half of this year, marking the next step after the 2nm family and positioning the foundry to extend its lead in advanced-node manufacturing for AI and high-performance computing chips.
Compared with the N2P process, A16 offers an 8 percent to 10 percent performance increase at the same power envelope, or a 15 percent to 20 percent power reduction at the same performance level, based on data TSMC has disclosed. The node also introduces Super Power Rail backside power delivery technology, which moves part of the power supply circuitry to the back of the wafer. That shift frees up routing resources on the front side and makes the process better suited for higher-power, larger-scale AI processors.
TSMC's A16 development has proceeded in parallel with N2 and N2P. The 2nm node entered risk production in late 2024, with volume production expected in the second half of 2025. N2P, a performance-enhanced variant, follows roughly six months later. A16 was always intended as the next major inflection point, adding backside power delivery to the nanosheet transistor architecture that debuted at 2nm. Industry sources indicate that A16's development verification phase — including test chip tape-outs, yield learning, and process window characterization — has concluded without major surprises.
Samsung Pushes SF1.4 to 2029, Prioritizes 2nm Yield
Samsung Electronics, the second-largest pure-play foundry, has taken a different approach. The company is focusing on its SF2 series 2nm process and has secured long-term orders from customers including Tesla for AI chips. However, Samsung recently adjusted its advanced process roadmap, postponing the SF1.4 (1.4nm-class) process — originally slated for 2027 — to 2029. The Korean firm will prioritize improving 2nm yields and commercialization capabilities over the next few years.
At the 2026 Next-Generation Lithography + Patterning Conference, Samsung Foundry presented its updated roadmap. The company confirmed that high-NA EUV lithography will enable 1nm-class and smaller nodes in 2030 and beyond, but the near-term focus remains on making SF2 a viable high-yield offering. Samsung has also introduced SF2P and SF2Z variants, with SF2Z incorporating backside power delivery similar to TSMC's Super Power Rail. The delay of SF1.4 to 2029 suggests Samsung is choosing to perfect its 2nm family before chasing the next node.
In the first quarter of 2026, Samsung's global foundry revenue share was approximately 7 percent, leaving a clear gap with TSMC's share of over 70 percent. Samsung is benefiting from order spillovers caused by TSMC's tight capacity, but its adjusted roadmap means the competition for sub-2nm processes now tilts toward TSMC's A16 timeline. The yield challenge at 2nm is industry-wide; Samsung's decision to extend the 2nm family rather than rush to 1.4nm reflects a pragmatic assessment of where volume revenue will come from over the next three years.
Intel's 18A and 14A on Track, but Mass Production Lags
Intel is pursuing a separate path. The company is advancing Intel 18A (about 1.8nm-class) and its upgraded 18A-P, which have entered early manufacturing stages. Its next-generation Intel 14A (1.4nm-class) is planned to enter risk production in the second half of 2027 and achieve mass production in 2028.
On paper, Intel 14A is nominally a step ahead of TSMC's A16 in node naming, but its mass production timeline is expected to arrive about two years later. Whether Intel can secure enough major external foundry customers remains a key focus for the market. Intel Foundry Services has signed design wins, including a multi-generation agreement with Amazon Web Services for custom Xeon chips and a deal with Microsoft for a custom compute chip, but volume ramps at 18A and beyond will determine if the business can meaningfully challenge the TSMC-Samsung duopoly.
Intel's 18A introduces RibbonFET gate-all-around transistors and PowerVia backside power delivery — both firsts for Intel. The process is being manufactured at Intel's Fab 52 and Fab 62 in Arizona, as well as in Ireland. The company has stated that 18A is on track for risk production in 2025 and volume in 2026, with 18A-P following as a performance-optimized variant. The two-year gap to 14A mass production underscores the increasing difficulty of each node shrink and the capital intensity required to sustain it.
Why the Timing Advantage Matters
AI chips are becoming one of the most important growth markets for advanced process nodes. If A16 enters mass production in the fourth quarter as planned, TSMC could secure a batch of high-end AI and HPC orders before Samsung and Intel ramp their next-generation processes. Advanced processes have also become a pillar of TSMC's future revenue growth. As N2, N2P, and A16 scale up successively, higher unit prices at these nodes are expected to increase the revenue contribution from AI and further consolidate TSMC's dominant market share.
The gap is already substantial. In Q1 2026, TSMC held more than 70 percent of global foundry revenue, while Samsung held roughly 7 percent. Both competitors still need to prove their new processes can achieve stable high-yield mass production and fulfill orders from large-scale customers. TSMC's July 2026 revenue jumped 45 percent year-on-year to NT$256.9 billion, driven by strong AI chip demand, reinforcing the financial advantage that funds its aggressive capacity expansion.
Customer demand for AI accelerators has created a structural shift in foundry economics. Training and inference chips for large language models require massive die sizes, high power density, and advanced packaging — all of which favor the most advanced nodes and the foundries that can deliver them reliably. TSMC's CoWoS-L and SoIC packaging capacity is fully booked well into 2026, and the company is expanding advanced packaging capacity in Taiwan and Japan to meet demand.
Backside Power Delivery Becomes the Differentiator
The Super Power Rail technology in A16 is part of an industry-wide shift toward backside power delivery networks (BSPDN). By routing power from the back of the wafer, manufacturers reduce IR drop, free up front-side metal layers for signal routing, and improve density for high-performance designs. Intel's 18A also uses a backside power scheme called PowerVia, while Samsung plans to introduce its version with SF2Z and SF1.4.
The race is no longer just about lithography resolution. Power delivery, thermal management, and advanced packaging — such as TSMC's CoWoS and SoIC, Samsung's SAINT, and Intel's EMIB and Foveros — are becoming co-equal differentiators. TSMC's ability to deliver A16 with Super Power Rail on schedule will test whether its integration of these technologies can maintain the cadence that has defined its foundry leadership.
This integration challenge extends beyond the foundry walls. EDA tool vendors, IP providers, and design houses must all update their flows to support backside power delivery and the new design rules it entails. TSMC has been working with Synopsys, Cadence, and Siemens EDA to qualify A16 design kits, and early access customers have been running test designs through the flow since mid-2025. The ecosystem readiness for A16 is further advanced than for competing nodes at a similar stage, another factor that could accelerate customer adoption.
For the broader semiconductor supply chain, the message is clear: TSMC's process cadence remains the benchmark. Samsung's delay to 2029 for 1.4nm and Intel's 2028 target for 14A mass production give TSMC a window to lock in the next wave of AI accelerator designs. Whether that window translates into durable market share gains depends on execution — yields, capacity, and the ability to co-optimize process and packaging for the most demanding customers.
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Sources
Supply chain reports cited by TradingKey; TSMC public guidance on A16 timeline; Samsung roadmap updates from NGL conference; Intel 18A/14A roadmap disclosures.