Samsung Pushes High-NA EUV Adoption to 1nm Node Around 2030 as Intel Races Ahead
Samsung Electronics has confirmed it will delay the commercial deployment of ASML's High-NA EUV lithography until its 1nm process node, expected around 2030, marking a decisive split in strategy among the world's three leading foundries. The move leaves Intel as the only chipmaker currently using the next-generation lithography in high-volume manufacturing, while TSMC says its 2029-era nodes will not require it.
The timeline emerged from the Next-Generation Lithography + Patterning Conference (NGL 2026) in Suwon, where a Samsung delegate told ZDNet Korea that the company originally hoped to introduce High-NA EUV at the 2nm and 1.4nm nodes. "We wanted to introduce high-NA EUV into volume production at the 2nm and 1.4nm nodes, but further technical improvements are still needed," the executive said. "We believe high-NA EUV will become necessary starting with A10 and beyond, and we're conducting joint development with a variety of partners."
A Fracturing Consensus
For years, the industry treated High-NA EUV — which raises the numerical aperture from 0.33 to 0.55 — as an inevitable stepping stone for every foundry pushing past 3nm. The higher aperture improves resolution and can replace multiple conventional EUV patterning steps with a single exposure, potentially lowering cost and cycle time for the most critical layers. But the tools cost upward of $300 million each, demand new mask and pellicle ecosystems, and impose tighter depth-of-focus constraints that complicate high-volume manufacturing.
Samsung's decision to pause reflects those realities. The company installed its first High-NA system at Hwaseong in 2025 and added a second in the first half of 2026, an investment estimated at over KRW 1 trillion. Yet an earlier Chosun Ilbo report noted that commercial deployment remains on hold, as bringing the technology into full-scale production would significantly increase costs while Samsung works to turn around its foundry business.
Intel's Lone Bet
Intel, by contrast, has already crossed the threshold. At its 2026 VLSI Symposium presentation, the company disclosed that High-NA EUV is being used for selected layers of its Intel Core Ultra Series 3 processors, codenamed Panther Lake, manufactured on the 18A process. ASML confirmed the milestone, calling it the semiconductor industry's first use of High-NA EUV in mass-produced logic devices.
The move aligns with Intel's broader foundry push under CEO Lip-Bu Tan. The company reported in July that 18A yields have climbed to roughly 85%, up from about 65% earlier in the year, and says it has secured foundry commitments from multiple customers for the second half of 2026. If those yields hold, Intel's early High-NA experience could become a competitive differentiator as it courts external design houses. The company has also signaled that its 14A process, the successor to 18A, will lean even more heavily on High-NA EUV for critical layers, extending the lead it is building today.
TSMC's Measured Pace
TSMC, the market leader, is charting a third path. Chairman and CEO C.C. Wei told TechNews in June that the company has purchased High-NA equipment and is actively conducting R&D. But Senior Vice President Kevin Zhang, speaking to Tom's Hardware, said TSMC's upcoming A13 and A12 processes — both targeted for 2029 — are not expected to require High-NA EUV. Conventional EUV multi-patterning, refined through years of production learning, remains sufficient for those nodes in TSMC's view.
The divergence is striking. Three companies, all with High-NA tools on their floors, have arrived at three different deployment timetables. Intel is in production. Samsung is targeting 2030. TSMC is keeping the option open but sees no urgency before 2030 at the earliest. Some analysts argue that TSMC's massive volume gives it unique advantage to optimize conventional EUV multi-patterning in ways smaller foundries cannot, effectively delaying the economic crossover point where High-NA becomes mandatory.
The Memory Angle
The split extends beyond logic. SK hynix, the world's second-largest memory maker, introduced its first mass-production-grade High-NA system in the second half of 2025 and began R&D this year, according to a separate ZDNet report. The company is evaluating both conventional EUV multi-patterning and High-NA single patterning for future advanced DRAM processes, while also exploring phase shift masks (PSMs) to further improve EUV resolution.
PSMs create phase differences in the light forming adjacent circuit patterns, improving contrast and enabling clearer patterning of extremely fine features. SK hynix is also investigating how PSM technology could be further developed for High-NA EUV, suggesting that memory makers may adopt the technology on a different cadence than logic foundries.
Micron and Samsung's memory divisions are also tracking High-NA development closely, though neither has publicly committed to a deployment timeline. The memory industry's regular half-pitch scaling cadence — typically ahead of logic by a node or two — means DRAM makers will feel the resolution pressure sooner, potentially forcing an earlier High-NA decision than the logic foundries face.
Cost and Ecosystem Gaps
The economic case for High-NA remains contested. Each tool costs roughly 2.5 times a conventional EUV scanner. Masks for High-NA are more complex and expensive, and the pellicle — a thin membrane that protects the mask from particles — must withstand higher thermal loads without degrading image quality. ASML reached a new readiness milestone in 2026, but the supply chain for these consumables is still maturing.
Samsung's delegate at NGL 2026 acknowledged that "related technologies such as masks and pellicles still need to advance." The company is also expanding its use of Atomic Layer Etching (ALE) as a complementary technique. According to Sisa Journal, ALE addresses the growing difficulty of precisely patterning increasingly narrow circuit features using conventional plasma-based etching alone — a challenge that exists regardless of lithography choice.
Beyond the tool itself, the High-NA ecosystem requires new resist materials, metrology solutions, and inspection systems capable of catching defects at the finer resolution the technology enables. Several suppliers have told industry analysts that volume production of these consumables will not be fully qualified until late 2027 at the earliest, adding another gating factor for any foundry considering an early move.
What Comes Next
The practical implications will unfold over the next several years. If Intel's 18A ramp meets its yield and customer targets, the company will have proven that High-NA EUV can work in high-volume logic manufacturing years before its rivals commit. That could strengthen Intel Foundry's pitch to fabless customers who need the most advanced nodes.
If TSMC's conventional EUV multi-patterning continues to deliver the density and yield its customers expect at A13 and A12, the pressure to adopt High-NA diminishes — and the cost advantage of staying on proven tools compounds. TSMC has also indicated that its N2 node, entering volume production in 2025, will rely entirely on conventional EUV, giving the company years of additional production data before any High-NA transition.
Samsung's 2030 target for its A10/1nm node aligns with its public roadmap: 2nm commercialization in 2025, 1.4nm SF1.4 mass production in 2029, followed by SF1.4+ and 1nm in 2030. The question is whether the foundry market will still be a three-horse race by then, or whether the economics of High-NA will have reshaped the competitive picture. Geopolitical factors — from U.S. export controls on advanced lithography to the CHIPS Act funding flows — will also shape which company's timeline prevails in practice.
For now, the industry's most expensive lithography tool has become a strategic lever rather than a universal requirement. Intel is betting that early mastery pays off. TSMC is betting that patience and incremental improvement on conventional EUV will win. Samsung is betting that it can afford to wait until the ecosystem matures and its own foundry turnaround is complete.
The only certainty is that the next decade of semiconductor scaling will be defined not just by physics, but by which company's bet on High-NA EUV proves correct.
TrendForce report on Samsung's High-NA EUV timeline
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