Samsung Falls In Line: Foundry Giant Delays High-NA EUV Adoption Until 2030
By Tech Desk | August 2026 — Samsung Foundry, the world's second-largest semiconductor manufacturer by production capacity, has officially delayed its High- Numerical Aperture (High-NA) EUV lithography adoption until 2030, industry sources confirm. The decision places Samsung as the last of the three leading foundries — TSMC, Intel, and Samsung — to commit to ASML's newest top-tier lithography tools, with TSMC expected to begin volume production with High-NA EUV in 2029 and Intel already scaling its 14A node with the technology.
Why the Timing Matters
The foundry industry's transition to High-NA EUV represents the most notable leap in lithography capability since the introduction of conventional EUV in 2019. By increasing the numerical aperture from 0.33 to 0.55, High-NA EUV delivers four times the resolution of its predecessor, enabling transistor gates below 10 nanometers in a single exposure — eliminating the multi-patterning complexity that has plagued leading-edge node development.
"High-NA EUV is not just a incremental improvement; it's a fundamental platform shift that redefines what's possible in chip design," said Naga Chandrasekaran, executive vice president and general manager of Intel's factory division, during ASML's recent earnings call. "Intel is committed to integrating high-NA tools into our 14A and future processes to restore process leadership."
Intel's eagerness contrasts sharply with Samsung's more cautious approach. According to ZDNet Korea, Samsung had hoped to introduce High-NA EUV at its 2nm and 1.4nm nodes, but further technical improvements are still needed, with the technology now expected to become necessary from the A10 node and below. Samsung has already commercialized its 2nm process and plans to begin mass production of its 1.4nm SF1.4 process in 2029, followed by SF1.4+ and 1nm in 2030.
Technical Challenges Beyond Resolution
While the resolution gains are compelling, ZDNet notes that the technology remains "challenging and expensive." The increased aperture demands substantial upgrades across the entire manufacturing ecosystem:
- Masks and pellicles: High-NA EUV masks require new manufacturing techniques, and pellicle contamination has been a persistent issue in early deployments
- Alignment accuracy: The tighter tolerances require more precise alignment systems across the production line
- Illumination optics: The optical path requires re-engineering to maintain coherence across the broader numerical aperture
- Scanner throughput: High-NA tools currently carry lower wafer throughput than conventional EUV, impacting overall fab productivity
"Related technologies such as masks and pellicles still need to advance," the ZDNet report emphasizes. "Conventional EUV multi-patterning and High-NA EUV single patterning are therefore examined in parallel — the industry is not abandoning the older approach but evaluating when the trade-off shifts in favor of High-NA single patterning."
Industry Overview: TSMC Leads, Intel Follows, Samsung Lagging
The three foundries' High-NA EUV adoption timelines reveal a strategic divergence:
| Foundry | Current Status | Planned Introduction |
|---|---|---|
| Intel | Already integrating into 14A node | Ongoing risk production |
| TSMC | Resisting initially; now engaging | 2029 volume production |
| Samsung | Last to commit | 2030 (1nm node) |
Intel's accelerated adoption stems from its foundry transition strategy. After losing process leadership to TSMC in the sub-10nm era, Intel has pinned its comeback on High-NA EUV as a differentiating capability. The company's IDM 2.0 strategy positions high-NA capability as a key selling point for both internal production and foundry customers.
TSMC's stance has evolved notably. Earlier this year, the Taiwanese giant was publicly resistant to High-NA EUV adoption, citing cost-benefit concerns and the sufficiency of conventional EUV multi-patterning for its roadmap. However, industry sources indicate that ASML's persistent engagement and Intel's public commitment have persuaded TSMC to accelerate its own timeline. The company is now expected to introduce High-NA EUV in 2029 for its most advanced nodes, positioning it just one year behind Intel's 14A integration.
Samsung's delayed adoption reflects a calculated risk. The company's foundry division has been "consistently upgrading its chip-making tools," as Design And Reuse reports, and currently delivers competitive yields with existing Low-NA EUV tools. ZDNet Korea's sources suggest Samsung is in no rush, as its existing tool fleet adequately supports its 2nm and upcoming 1.4nm volume production. By waiting until 2030 — which Design And Reuse identifies as "one of the last introductions of High-NA EUV machinery across leading-edge semiconductor node designs" — Samsung avoids the early-deployment premium while still accessing the technology before its most advanced roadmap nodes require it.
Cost-Benefit Analysis: When Does the Trade Shift?
The industry's central question is whether the resolution advantage of High-NA EUV justifies its estimated 2-3x higher tool cost and operating expense. For logic chips at nodes below 10nm, the answer appears to be yes — single patterning replaces multi-patterning steps, reducing alignment steps, mask changes, and process complexity. For memory manufacturers like Samsung HBM production, the calculus may differ.
"Samsung being one of the last does not necessarily mean the company is in a rush, as it is currently performing well with the existing Low-NA EUV tools," the Design And Reuse analysis notes. "Samsung Foundry has been consistently upgrading its chip-making tools."
TSMC's expected 2029 introduction and Intel's ongoing 14A integration will create a three-year adoption window during which Samsung can evaluate yield data, cost structures, and customer demand before committing its own feline. The 2030 target for Samsung's 1nm node coincides with an industry-wide inflection point where an increasing volume of logic and memory products will require the enhanced resolution that only High-NA EUV can provide commercially.
Supply Chain Implications
The staggered adoption timeline has ripple effects across the semiconductor supply chain. ASML's delivery schedule has already been adjusted to prioritize Intel's 14A ramp, with TSMC's 2029 bookings shaping the second quarter of the decade. Samsung's 2030 commitment represents a smaller initial order batch, but still constitutes a meaningful portion of ASML's long-term revenue visibility.
Equipment manufacturers, mask suppliers, and materials companies are similarly adjusting their roadmaps. Companies that built their High-NA readiness strategies around a 2027-2028 industry-wide adoption may need to revise their deployment timelines and potentially delay or re-scope related capital investments.
Conclusion: A Three-Foundry Roadmap Taking Shape
The foundries' High-NA EUV adoption timeline — Intel leading in 2024-2025, TSMC following in 2029, and Samsung committing in 2030 — illustrates how a single technology transition is unfolding differently across the industry. The common thread is that High-NA EUV is no longer optional for leading-edge manufacturing; it is becoming a required capability for nodes at 10nm and below.
For Samsung, the 2030 target provides a deliberate runway to validate the technology at volume, optimize cost structures, and ensure a smooth transition for its foundry customers. For the industry at large, the three-year spread mitigates the risk of a simultaneous capacity crunch at ASML's Veldhoven fabrication facility and gives fabs time to adjust their production planning and customer commitments.
As the 2030 deadline approaches, all eyes will be on whether Samsung's caution was strategic restraint or delayed necessity. The next five years will see Intel and TSMC validate High-NA EUV at scale, providing the yield data and cost structures that will ultimately determine whether Samsung's 2030 adoption target proves prudent or precipitous.
Keywords: semiconductor, foundry, High-NA EUV, Samsung, TSMC, Intel, ASML, lithography, 2nm, 1nm, chip manufacturing
Silicon chip close-up — representative of the advanced manufacturing processes discussed in this article.
Circuit board detail — illustrating the nanoscale features High-NA EUV lithography enables.
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