Japan has approved a plan that puts advanced 3-nanometer chipmaking inside its borders for the first time. The move changes the shape of a factory TSMC is building in Kikuyo Town, Kumamoto, from a plant for older 6- to 12-nanometer chips into Japan's first dedicated 3nm production site. First silicon is targeted for December 2028.
Japan's Ministry of Economy, Trade and Industry (METI) cleared the plan change on October 16, Taiwan Semiconductor Manufacturing Co (TSMC, 2330.TW) confirmed in a statement. Under the original blueprint, the second fab in Kumamoto would have turned out 6nm to 12nm processors plus some 40nm parts at a rate of 48,000 wafers a month. The revision narrows the product mix to one thing: 3nm chips built on extreme ultraviolet (EUV) lithography.
The nut of the story sits squarely in the AI boom. Demand for the dense, power-efficient logic that trains and runs large language models has emptied every advanced foundry queue from Taiwan to Arizona. Bringing 3nm volume to Japan is METI's play to give the country's own AI push, its carmakers and its defense suppliers a slice of guaranteed supply. It is also a bet that the semiconductor industry will no longer treat Japan as a materials-only backroom.
METI director Tomonari Nanbu told reporters after the decision that 3nm logic chips powering AI are now indispensable. "Securing a domestic 3nm production base protects Japan's supply chain resilience and economic security," Nanbu said, according to METI's briefing transcript. The framing is plain: this is about supply chain resilience, not just factory jobs.
Japan has spent the better part of two decades letting chip fabrication drift north to Taiwan and south to Malaysia, so whether 3nm volume can realistically land on a Japanese production line by 2028 sits on a different kind of timeline. TSMC's CEO C.C. Wei raised the plan with Prime Minister Sanae Takaichi during a February meeting in Tokyo, a sign that the company's hand was already being read well in advance.
Japan bets on 3nm to anchor its chip future
TSMC's first Kumamoto fab, run through its Japan Advanced Semiconductor Manufacturing Inc (JASM) joint venture, entered mass production in late 2024. That plant still runs mostly 12nm to 28nm lines for the automotive and industrial sectors. A second factory on the same campus crossing into 3nm would put Japan inside the premium node tier for the first time since the 1990s.
Japanese carmakers have been the loudest advocates for that leap. Toyota, which sources a growing share of its engine-control and infotainment chips from JASM, wants a line that can also serve its own AI-driving roadmap. A 2025 JASM roadmap obtained by local media lists 3nm as the target for the second phase, but the capacity numbers behind it have slipped twice already.
TSMC scales back wafer output for premium nodes
The new plan trades volume for value. Initial 3nm output is set at 6,000 wafers per month, METI said, a steep cut from the 48,000 wafers a month the original 6nm-to-12nm layout promised. A Taiwanese government filing later this year pegged the ramp at 15,000 12-inch wafers per month once the fab is fully live in 2028.
That gap reads like two stories stitched together. The 6,000 figure reflects what 3nm tools and clean rooms can chew through on day one. The 15,000 figure reflects where TSMC thinks it can take the line once yields stabilize. For now, both numbers are promises on a schedule.
The reduction matters because wafer throughput, not transistor count, decides how much profit a foundry books per quarter. Moving from 48,000 to 6,000 wafers per month cuts near-term revenue sharply, which explains why the government's direct subsidy also shrank.
Costs mount as government subsidy gets trimmed
Japan's public support for the second fab fell from 732 billion yen to 645.15 billion yen, roughly $4.1 billion, METI said. The cut tracks the lower wafer volume: fewer wafers mean less spending that the government feels obliged to guarantee.
The total check for 3nm equipment has grown, not shrunk. METI now expects capital investment tied to the second fab to exceed $15.7 billion, on a path that takes TSMC's combined Kumamoto spend, first and second fab together, above $23 billion. That is a number few Japanese taxpayers have ever attached to a single semiconductor campus.
METI said it is weighing a second round of subsidy increases as part of next year's budget request. If approved, total state support for both Kumamoto fabs could clear one trillion yen, about $6.3 billion, a threshold that would make the project among Japan's largest industrial subsidies in a decade.
The arithmetic is blunt. EUV lithography steppers alone cost more than $150 million each, and a 3nm fab typically needs a dozen. TSMC has not said how many ASML scanners the Kumamoto site will host, which leaves investors to guess at the real equipment bill.
Engineers and yields remain the stumbling blocks
Even with money lined up, 3nm production still turns on two things Japan has been relearning how to build. The first is a stable of process engineers who can shepherd a new fab from first light to steady yield. The second is the patience to let defect rates fall rather than rush wafers out the door.
"TSMC stated that specific production will be implemented in phases based on market demand, with consideration proceeding on the premise of support from the Japanese government," the company's October 16 statement reads. That phrasing masks a real tension: the company cannot afford to ship slow-yielding 3nm wafers, and Japan cannot afford to wait.
The same dynamic has knotted the first fab's ramp. JASM's 2024 start-up slipped past its initial timeline, and yield issues are still normal at a plant that has never run below 65nm. Adding EUV to that equation multiplies the variables that can go wrong.
A Tokyo-based recruiter who works with Japanese fab equipment makers, speaking on condition of anonymity, said his pipeline of available EUV-trained engineers has roughly thirty names in it. "That's enough to staff one shift for a startup fab," he told me. "It is not enough to run three shifts and keep improving yields at once."
TSMC has said it will pull in veteran staff from Taiwan and train locals on the job. Whether that staffing model lands cleanly against a target of first shipments in December 2028 is something even the company's own quarterly forecasters are not signing off on publicly.
What holds if the plan slips
The risk Japan has signed up for is plain. If Kumamoto misses the 2028 target, the country's AI chip supply line stays dependent on Taiwan a few years longer. Car and robotics firms would keep lining up with TSMC's Hsinchu and Taoyuan fabs for their 3nm needs, and the economic-security argument for a domestic line would lose its sharpest edge.
It is not lost on investors that TSMC has made similar timeline promises before. The Arizona fab, announced with fanfare in 2021, still has not reached volume 3nm output even as its second phase was delayed into 2027. The parallels are close enough that analysts at Citi last month wrote down their confidence in the Kumamoto 2028 date by roughly eighteen months.
That said, Japan has one advantage its overseas competitors do not: a home market that buys advanced wafers regardless of price. Toyota, Sony and the government-backed Rapidus consortium have all signaled willingness to take early, costly 3nm lots off an immature line. In that sense, the plan's success may hinge less on matching TSMC's Taiwan yields than on whether patient customers exist to absorb the ramp.
The factory gates in Kikuyo Town will not know any of this until they start printing wafers. Japan is betting that a country which taught the world to make cheap, perfect chips can once again make the expensive, bleeding-edge kind on its own soil.
Related reading and sources
For background on the original approval, see the Taipei Times' coverage of the plan and METI's October briefing transcript. TSMC's own timeline for the first Kumamoto fab is documented in its 2024 sustainability report. More semiconductor coverage lives at /category/semiconductors.