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Volume III Edition Daily

HBM4E Samples Ship as AI Memory Sells Out Before It Starts

Samsung shipped 12-high HBM4E samples in late May, and SK Hynix followed a few weeks later. The memory does not have a JEDEC standard yet, but the market does not care. Samsung says 2026 HBM4 volume is effectively sold…

Semiconductors 1,052 words 5 min read

HBM4E Samples Ship as AI Memory Sells Out Before It Starts — Semiconductors No Image Semiconductors
Lead image · Filed 22 October 2026, 03:04

Samsung shipped 12-high HBM4E samples in late May, and SK Hynix followed a few weeks later. The memory does not have a JEDEC standard yet, but the market does not care. Samsung says 2026 HBM4 volume is effectively sold out, and SK Hynix says its entire 2026 DRAM and NAND output is sold out. That is the state of AI memory in October 2026: supply is already gone before the next generation reaches mass production.

The numbers are concrete. HBM4E keeps HBM4's 2,048-bit interface and pushes per-pin rates to 14 to 16 Gbps. That yields roughly 3.6 TB/s per stack, about triple the ~1.2 TB/s of HBM3E. A 12-high stack holds 48 GB. Rambus calculates that six stacks deliver roughly 24.6 TB/s of aggregate bandwidth to an accelerator. Those are not projections. Those are the specs vendors are sampling now.

Semiconductor packaging diagram showing 2D, 2.5D, and 3D integration with HBM stacks

It isn't clear this will hold. No independent benchmark of HBM4E silicon has been published. Vendor claims on power efficiency vary: Samsung says 16% better energy efficiency and more than 14% lower thermal resistance; SK Hynix reports more than 20% better power efficiency and 17% improved heat resistance. Both are vendor numbers, not verified by third-party tests. And without a JEDEC standard, HBM4E is a vendor-defined generation for now, which means Samsung, SK Hynix, and Micron can ship meaningfully different implementations under the same label.

Memory is the bottleneck everyone missed

TSMC has started volume production of its 2nm (N2) node in early 2026. Apple has secured more than 50% of initial allocation for the A20 iPhone 17 family and M6 Mac chips. AMD's Zen 6 and EPYC Venice are reported to use N2 starting in the second half of 2026. The target is 60,000 wafers per month by Q4 2026, with N2P volume production scheduled for the second half of 2026.

But faster nodes do not help if the memory cannot feed them. TSMC also announced a 3 to 5 percent price increase across sub-5nm nodes effective FY2026, the first explicit hike since the 2024 cycle. It reflects rising EUV mask, wafer, and assembly costs. Those costs propagate through the AI chip stack, and memory is the part where demand most outstrips supply right now.

Silicon wafer close-up

The supply picture is tight by design. Memory inventories at Samsung and SK Hynix fell below 10 days of supply in early September 2026, according to Digitimes reporting. AI infrastructure spending is driving simultaneous demand for HBM4 stacks, DRAM, and NAND. Micron expects its own HBM4E volume production in calendar 2027. That is a full year from now, and by then the market will have moved to whatever comes after HBM4E.

Export controls tighten from both sides

The semiconductor story in October 2026 is not just about faster memory. On October 16, Beijing proposed export controls on 23 AI technologies, including AI models, agents, and computing clusters. The rules cover overseas deployment of AI models containing restricted technology, but exclude access through APIs, websites, apps, and software-as-a-service platforms. China's commerce ministry said the controls are partly intended to prevent misuse of systems capable of autonomously generating malicious software that threatens critical infrastructure.

This is part of a broader revision covering 40 technologies across AI, biotechnology, and solar power. Exporters must register overseas technology transfers from Friday, with final rules after public consultation closes November 15. The distinction between exported software and API access preserves international reach for companies like DeepSeek and Alibaba, while giving Beijing tighter oversight of sensitive technology transfers.

It is not just a China story. Washington's earlier export controls on China's access to cutting-edge American AI chips have kept U.S. firms Anthropic and OpenAI in the lead, though Chinese rivals are finding workarounds to narrow the gap. Meanwhile, Huawei continues to produce its Ascend AI chips on SMIC's N+2 process, roughly seven nanometers, which is about three generations behind TSMC's leading edge. Export controls reduce but do not eliminate Chinese frontier-chip capability.

The 2nm reality check

NVIDIA's first-generation Rubin AI training chip is reportedly on TSMC N3P, not N2, according to Presenc AI research from May 2026. The decision reflects N2 capacity reality: there simply are not enough wafers for Rubin volume in 2026, and reticle-stitched giant dies are cheaper on a more mature node. NVIDIA is reserving N2 for a later refresh. AMD, by contrast, has made N2 its marquee CPU play with Zen 6.

That split matters. It shows that even with 60,000 wafers a month, the most advanced node is already fully booked by one or two customers. Apple has more than half of it. The rest is divided between AMD, Qualcomm, MediaTek, and a small NVIDIA reservation for future use. Intel has limited foundry use. There is little room left for new entrants.

It's not clear whether HBM4E can close that gap. The samples are real, the qualification tests with Nvidia and major hyperscalers have reportedly passed according to KED Global reporting in early October, but neither Samsung nor Nvidia has officially confirmed that. If true, it means Samsung has cleared one of the toughest barriers in memory supply: getting a major accelerator vendor to validate the silicon before volume shipping. SK Hynix, by contrast, has remained Nvidia's primary HBM supplier and reportedly holds long-term agreements with around ten major customers.

What comes next

By late 2026, the chip industry's conversation is less about which node is fastest and more about whether the supply chain can feed the nodes that exist. TSMC's 2nm is here, HBM4 is in high-volume production, and HBM4E is on the bench. The 2026 HBM4 supply is sold out. The 2027 supply is already locked in at higher prices. And both China and the U.S. are tightening export rules on AI technology, which changes where chips can go and who can access them.

The next checkpoint is mass production timing for HBM4E. Samsung says it will align with customer schedules without naming a date. SK Hynix targets 2027. Micron points to 2027. If those dates slip, the gap between accelerator demand and memory supply widens. And with Apple holding more than half of TSMC's leading-edge wafers, the rest of the industry is competing for scraps.

Read more semiconductor coverage at desk coverage and follow the Reuters report on China's proposed AI export controls.