Samsung Turns to TSMC for Nvidia's Next-Generation HBM Base Die

Samsung Electronics will use TSMC's 3-nanometer process to manufacture the base dies for Nvidia's next-generation custom high-bandwidth memory (HBM) chips, a reported arrangement that would bring two of the world's most capable foundries together at the memory-manufacturing stage for the first time. Citing unnamed industry sources, the Seoul Economic Daily reported the plan Sunday, a reading later corroborated by Reuters; both outlets described the move as a strategic realignment of the AI hardware supply chain as chipmakers race to feed the compute appetite of large language models. The deal would have Samsung continue producing the memory-cell layers on its in-house six-generation DRAM line while relying on TSMC's 3nm node for the base die that houses Nvidia's custom memory controller — a split that, industry analysts say, reflects where yields and integration density are highest today.

The reported project centers on Nvidia's NVHBM, or custom HBM, technology that the company unveiled in August. Unlike standard HBM, where the memory controller lives on the GPU and consumes real estate on the accelerator's compute die, Nvidia's design moves that controller into the base die and stacks the memory layers on top. Per reporting from the Seoul Economic Daily, this relocation cuts the physical layer area by roughly 60% compared with standard HBM, widens memory bandwidth by up to 30%, and lowers power consumption by about 15% relative to a conventional seventh-generation HBM4E stack. Those margins matter because, as Semiengineering's weekly industry review noted, a growing share of AI training cost is no longer the model or the software but the physical movement of bits between compute and memory — an observation now echoed inside the foundry boardrooms of both Samsung and TSMC.

Nvidia has reportedly asked all three major HBM suppliers — Samsung, SK Hynix, and Micron Technology — to adopt TSMC's 3nm process for their NVHBM base dies and to pair it with a sixth-generation DRAM process for the memory dies themselves. Standardizing the process across suppliers should, in theory, let Nvidia validate one base-die tapeout and apply it to multiple memory vendors, an appealing simplification as the company scales production for its next-generation Blackwell-derived systems. Samsung is said to have accepted the requirement after an internal review, but it will retain its own in-house manufacturing flow for standard HBM parts and for custom memory built for other customers. The company is also said to be assessing whether its own foundry — which competes directly with TSMC at the leading edge — could produce the NVHBM base die if demand ever exceeds TSMC's 3nm capacity, a hedge that underscores how much is at stake.

For TSMC, the arrangement quietly expands its already dominant role in Nvidia's AI supply chain beyond the GPU and NPNVLink silicon. The Taiwan Semiconductor Manufacturing Co. already fabricates the bulk of the world's most advanced logic chips, including processors for Nvidia, AMD, and Broadcom as well as custom AI accelerators for Apple, Google, Amazon, Microsoft, Meta, and OpenAI. Industry executives have warned for months that capacity constraints could threaten technology companies' ambitious AI infrastructure investments, and that worry has made yield — not just raw wafer count — the decisive factor in process selection. The same analysts who track the foundry rivalry between Samsung and TSMC note that the industry puts TSMC's 3nm yield above 90%, while Samsung Foundry's comparable 2nm (SF2) process is said to sit near 60%, a gap that helps explain why Nvidia would steer its most yield-sensitive base die toward TSMC's line.

Samsung's decision fits a broader pattern already visible in 2026. Semiengineering's October 9 industry review reported that TSMC and GlobalFoundries had just inked a $2 billion manufacturing agreement covering silicon interposers for TSMC's CoWoS advanced-packaging ecosystem at GlobalFoundries' Malta, New York fab, with volume production targeted for the first half of 2028. The same review recorded that global semiconductor sales had reached $159.7 billion in August — up 8% from July and enough to push year-to-date sales past $1 trillion, according to figures compiled by the Semiconductor Industry Association and WSTS. McKinsey & Company, quoted in that review, expects inference to account for roughly 60% of AI compute by 2030, a forecast that directly drives demand for custom accelerators, HBM, chiplets, advanced packaging, and silicon photonics. Samsung's memory-testing investment of roughly $3.9 billion in Vietnam, also noted in the industry review, sits alongside this HBM-base-die decision as evidence that the company is choosing selective specialization over vertical integration on every node.

The numbers behind the deal

The bandwidth and power arguments that justify the base-die split also carry a supply-chain dimension. UBS, whose HBM demand model appeared in Seoul Economic Daily coverage, forecasts global HBM demand in 2027 at about 61.5 billion gigabits — up 91% from this year — while new shipments are expected to reach only 54.6 billion gigabits, implying a potential shortfall of roughly 10%. That gap is precisely what the Samsung-to-TSMC base-die arrangement appears designed to close: by letting Samsung pour the memory stacks on its established DRAM line and run the controller die through whichever foundry yields best, Nvidia and its partners can chase the bandwidth ceiling without betting the whole supply chain on a single process. For readers who track the category closely, the same dynamic plays out across the Semiconductors coverage area, where packaging, process, and yield decisions increasingly determine which AI systems ship and when.

Not every analyst frames the shift as purely technical. Some point out that Samsung and TSMC are, by design or not, competitors in the foundry market, so a reported cooperation at the HBM-manufacturing stage is as notable for its economics as for its engineering. Samsung is said to keep its in-house production model for standard HBM parts, and it continues to evaluate its own foundry as a fallback source — a posture that lets it monetize its memory strength while selectively leaning on a rival node where yields have repeatedly proven higher.

The arrangement also raises questions about how the memory stack as a whole is standardized. By integrating its custom memory controller into the base die and asking multiple suppliers to adopt the same 3nm process for that die, Nvidia is effectively turning HBM into a more modular architecture. Semiengineering's September 30 industry review already described the broader industry trend toward chiplet-based memory subsystems and silicon-interposer-based stacking, and the October 9 issue reported that the data-transfer speed of existing HBM was straining to keep pace with GPU compute speed — a bottleneck that Nvidia's base-die design was built to relieve.

Conclusion

What began as a yield and integration-density calculation has landed as the most significant foundry handshake in the AI memory market this week, and it may not end with Samsung and TSMC. If Samsung's own SF2 node matures and its 2nm yield climbs toward TSMC's 3nm level, the same base-die tapeout could flow back onto Samsung's line, giving the Korean manufacturer two paths to the same Nvidia contract. For Nvidia, a single process across suppliers reduces validation cost and tightens the feedback loop between controller design and memory packaging just as inference workloads demand both more bandwidth and less power per bit. The reported 10% supply shortfall projected by UBS means there is little room for another missed ramp. With volume production of the next-generation stack expected through 2026 and into 2027, the base-die split between Samsung's DRAM expertise and TSMC's leading-edge yield is quickly becoming the chokepoint that defines who wins the next round of AI accelerators.

References

1. Reuters, "Samsung Electronics," via the Seoul Economic Daily, October 18, 2026. Report on Samsung's plan to use TSMC's 3nm process for Nvidia's next-generation HBM base dies.
2. Taiwan News (Staff Writer Sean Scanlan), "Samsung to use TSMC process for Nvidia's next-generation memory chips," October 19, 2026. https://www.taiwannews.com.tw/en/news/7763248
3. Firstpost, "Samsung to use TSMC's 3nm process for Nvidia's next-generation HBM chips: Report," October 19, 2026. Report citing the Seoul Economic Daily.
4. Semiengineering (The SE Staff), "Chip Industry Week In Review," October 9, 2026. Coverage of the TSMC-GlobalFoundries $2B interposer pact, August global semiconductor sales of $159.7B, and McKinsey's inference-to-compute forecast. https://www.semiengineering.com/chip-industry-week-in-review-159/
5. UBS research, as cited by the Seoul Economic Daily, October 19, 2026. HBM demand and supply forecasts for 2027.
6. Wilson Center analysis, as quoted by Semiengineering, October 9, 2026. On data-transfer speed constraints between GPU compute and HBM.