AMD finally pulled the wraps off its first Zen 6 server chip this week at the AAI 2026 conference, and the numbers are eye-popping. The Epyc 9996 — codenamed "Venice" — packs 256 cores and 512 threads on a single socket, built on TSMC's N2 process. That's up from 192 cores on the previous-gen Turin. The chip carries a massive 1,024 MB of L3 cache — nearly triple the Epyc 9965's 384 MB — and AMD says it beats Intel's top Xeon 6980P by up to 3.4 times on AI agent workloads. Against Nvidia's recently announced Vera chip, AMD claims a 20 percent lead in per-core integer performance.
AMD's corporate VP of compute and enterprise solutions, Ravi Kuppuswamy, made clear during the keynote that Venice isn't one product. "It's a portfolio," he said. AMD has split the Epyc 9006 family into three tiers: the main Venice lineup on the SP7 socket, a mid-range SP8 variant arriving in the first half of 2027, and Venice-X with 3D V-Cache landing in the second half of 2027.
The SP7 Venice scales from 8 cores all the way up to 256. The top-end Epyc 9996 runs at a 600W TDP with a 2.55 GHz base clock and 4.1 GHz boost. That matches the power budget of Nvidia's Vera but delivers more than double the core count. A 96-core high-frequency SKU — the Epyc 9686F — hits 5 GHz boost, matching Intel's best turbo speeds for Granite Rapids.
A Portfolio, Not a Single Chip
The Venice product stack spans more than 30 SKUs. At the top sits the Epyc 9996 with 256 Zen 6c dense cores, 1,024 MB of L3, 16-channel MRDIMM support at 12,800 MT/s, and 128 PCIe 6 lanes in 1P config. Below that, the Epyc 9966 offers 192 cores at a 600W TDP with 768 MB of cache. The Epyc 9756 drops to 128 cores at 500W, while the 96-core Epyc 9686F targets frequency-optimized workloads with 5 GHz boost.
It's a big jump from Turin. The previous-gen Epyc 9965 — also 192 cores — used 12-channel memory at 6,400 MT/s and topped out at 500W. Venice brings 16-channel memory, PCIe 6, and MRDIMM speeds that AMD says deliver 1.6 TB/s per socket — nearly triple Turin's 576 GB/s and 33 percent more than Nvidia Vera's 1.2 TB/s.
Critically, all Venice chips are built on TSMC's N2 node. Each CCD holds 32 Zen 6c cores with 4 MB of L3 per core — double what Turin offered. Two I/O dies handle memory and PCIe traffic, and the design scales to eight CCDs per socket for the 256-core flagship.
Benchmark Blitz at AAI 2026
AMD published a full suite of benchmarks at the conference. On the TPCx-AI benchmark — which measures AI use cases processed per minute — the Epyc 9996 scored 5,982.91. That is more than triple Intel's Xeon 6980P at 1,750.36 and 73 percent ahead of AMD's own Epyc 9965 at 3,458.79. AWS's Graviton5 managed 2,444.8, putting AMD well ahead of Arm-based competition too.
In the FAISS vector similarity search using Meta's open-source library, Venice hit 751,453 queries per second. That compares to 316,069 for Intel's Xeon 6980P and 472,079 for the Epyc 9965. The Graviton5 lagged at 119,179 QPS. FAISS is widely used in AI agent pipelines for embedding search and retrieval-augmented generation, so gains here directly translate to faster AI applications.
On NGINX web serving with the WRK load generator, AMD claims a 2.8x improvement over Intel and 1.2x gen-on-gen over Turin. The raw numbers tell the story: the Epyc 9996 handled 28,789,170 requests versus Intel's 10,162,179 and Turin's 24,320,476.
Enterprise and Legacy Workloads
For enterprise tools, AMD reported a geomean of TPC-H, TPC-C, and Redis throughput numbers. The Epyc 9996 scored 6,054,748 — a 2.6x advantage over Intel's 2,284,701 and 1.6x over Turin's 3,867,149. In vectorized workloads using FAISS, the Venice delivered 751,453 QPS, beating Intel by 2.4x and Turin by 1.6x.
AMD also tested five different AI agent personas replayed across the chips. Here the Venice showed a 1.5x gen-on-gen improvement and a 2.5x lead over Intel's 6980P. While AMD didn't publish the raw metrics for the agent tests, the geomean throughput figures align with the pattern seen in the other benchmarks.
In SPEC CPU 2017 SPECrate integer testing, AMD used the 128-core Epyc 9756 to demonstrate per-core performance against Vera. AMD says it used Nvidia's published results and the same GNU 15.2 compiler for an apples-to-apples comparison. The 96-core high-frequency Venice showed a 20 percent per-core advantage over Vera at the same 600W TDP. Against Intel's 6980P, the 128-core Venice delivered 2x throughput and 1.3x per-core performance.
Memory Architecture: The Bandwidth King
One area where AMD is making a big bet is memory bandwidth. Venice SP7 scales to 16 memory channels with support for MRDIMMs at 12,800 MT/s or standard DDR5 RDIMMs at 8,000 MT/s. AMD claims per-socket bandwidth of 1.6 TB/s — higher than Nvidia Vera's 1.2 TB/s (24-channel LPDDR5X) and nearly triple Turin's 576 GB/s (12-channel DDR5 at 6,400 MT/s).
Intel recently enabled 8,000 MT/s RDIMMs on select Granite Rapids and Clearwater Forest SKUs, and says MRDIMM support at 8,800 MT/s lands in Q1 2027. AMD already ships MRDIMM support at 12,800 MT/s. For memory-bandwidth-bound workloads like AI inference, database analytics, and in-memory computing, that gap matters.
The SP8 Venice variant — arriving in H1 2027 — targets smaller deployments with 8 to 128 cores, 8-channel memory, and the same PCIe 6 implementation. AMD says this socket is designed for cost-sensitive edge and mid-range data center deployments.
How Venice Stacks Up Against Nvidia Vera
Nvidia published its first SPEC CPU 2017 results for Vera just days before AMD's Venice unveiling. AMD ran head-to-head tests using the same compiler and flags. With the 256-core dense Venice, AMD claims a 2.2x lead over Vera in SPECrate integer throughput. More notably, the 96-core high-frequency Venice beat Vera on per-core integer performance by 20 percent — meaning even a lower-core-count Venice part can outperform Nvidia's host processor on a per-thread basis.
That matters because Nvidia has been positioning Vera as the CPU node for its AI server platforms, paired with Blackwell or Rubin GPUs. Vera uses 72 custom Arm cores with 24-channel LPDDR5X. AMD's counter is Verano — a Venice variant on the SP8 socket packing up to 72 cores, 5 GHz peak clocks, and 24-channel LPDDR5X using SOCAMM2 modules. Kuppuswamy jokingly called it "Vera-No" during the keynote, making clear AMD intends to compete head-on for the AI host processor slot.
The Bigger Picture for Data Centers
AMD is positioning Venice as an agentic AI workhorse, but the performance gains spill into traditional data center workloads too. Code compilation, media processing, high-concurrency networking, and SQL databases all see substantial jumps on the new architecture. NGINX at 28.8 million requests per second, TPC-H query throughput at 2.6x over Intel — these aren't AI-only wins.
The timing is deliberate. Cloud providers are racing to deploy AI inference at scale, and the CPU remains the backbone of request routing, data preprocessing, and retrieval-augmented generation pipelines — all tasks where Venice's 256 cores and enormous cache can flex. AWS, Microsoft Azure, and Google Cloud are all expected to offer Venice-based instances within the next two quarters, according to AMD's partner briefings.
For enterprises running their own infrastructure, the Venice stack simplifies procurement. The SP7 socket covers everything from 8-core entry servers to 256-core monsters, meaning a single platform investment can span years of capacity growth. AMD says SP7 will be supported across at least two more CPU generations after Venice.
What Comes Next
Venice SP7 chips start sampling this quarter with volume production slated for Q1 2027. The SP8 variants follow in H1 2027, and Venice-X with up to 1,152 MB of 3D V-Cache arrives around H2 2027. Meanwhile, Intel's Granite Rapids and Clearwater Forest Xeons will have to contend with a chip that AMD says beats them on nearly every metric — and Nvidia's Vera has a 20 percent per-core gap to close.
AMD also confirmed that Zen 6 consumer CPUs are in the pipeline. While the 32-core CCD design has sparked speculation about a 32-core Ryzen part, AMD hasn't confirmed consumer Venice derivatives yet. The company's focus for now is clearly on the data center, where Epyc has been steadily eating into Intel's market share quarter after quarter.
For more semiconductor industry analysis, check out our Semiconductors category. AMD's full Venice benchmark data and SKU table are published at Tom's Hardware.