TSMC Posts Record Quarter as AI Demand Pushes Growth Past 40%

Taiwan Semiconductor Manufacturing Company delivered the most profitable quarter in its history this week, reporting second-quarter 2026 revenue of $40.2 billion, a 36% jump from a year earlier, and lifting its full-year growth target above 40%. The results confirm what the AI labs have insisted for months: the infrastructure spending cycle many expected to peak in 2026 instead accelerated, and the fab that makes the chips sits at the center of it. For a single company to post these numbers on the back of one customer segment is itself a remark about where the world's capital is flowing.

Net profit surged 77.4% to NT$706.56 billion, extending TSMC's run of double-digit profit growth to nine straight quarters. Gross margin reached 67.7%, above the company's own guidance ceiling, a direct reflection of the pricing power that comes from holding roughly 73% of the global advanced foundry market with no near-term challenger for the customers that matter. When one company makes the leading-edge silicon for nearly every AI accelerator on earth, its earnings are a weather vane for the whole industry, and the forecast reads expansion.

AI is now two-thirds of the wafer business

The clearest single measure of how thoroughly AI reshaped chip demand is TSMC's revenue mix. High-performance computing, the segment anchored by data-center AI accelerators, rose 20% in a single quarter and now accounts for 66% of total wafer revenue. Smartphones, which led TSMC's sales as recently as 2022, fell to 22%. The center of gravity moved, and it moved fast, in a way that no one in the handset era would have predicted a few years ago.

Advanced nodes drove almost all of that shift. The 3-nanometer process made up 30% of wafer revenue, with 5-nanometer adding 33%. Nodes at 7nm and below represented 77% of all wafer revenue, a concentration of value at one company's leading edge that has no historical precedent. The money is where the smallest transistors are, and the smallest transistors are where the AI accelerators live, so the two facts are the same fact seen from different angles.

The 2nm break is real

The quarter also marked the first meaningful commercial revenue from N2, TSMC's 2-nanometer node, at 3% of wafer revenue as the firm moved from engineering samples to paying production. N2 is not a shrink of the old design. Every chip TSMC built through 3nm used a FinFET transistor, a vertical silicon fin wrapped on three sides by the gate. N2 switches to a gate-all-around nanosheet, where three horizontal silicon ribbons are fully encircled by the gate, a structural change rather than a tweak.

The four-sided gate kills the leakage path that worsens as fins shrink. The payoff is concrete: N2 switches 15% faster, or uses 30% less power at the same speed, than N3, with more than 15% better transistor density and an 11% gain in on-chip memory density. The trade is a steeper yield curve and a margin dip of 3 to 4 points as volume ramps in the second half of 2026, the cost of breaking a transistor architecture that had been refined for over a decade and betting the roadmap on a new one.

CoWoS is the real bottleneck

TSMC's CoWoS advanced packaging, chip-on-wafer-on-substrate, bonds AI logic dies to stacks of high-bandwidth memory on a silicon interposer, lifting memory bandwidth from roughly 1 TB/s to over 3 TB/s. It is why NVIDIA's Blackwell, AMD's MI series, and every custom Google, Amazon, and Microsoft accelerator work at all, because the tight coupling of logic and memory is what makes large models run without stalling on data movement.

It is also sold out. Lead times run 52 to 78 weeks, and the constraint is structural: the interposer is itself a wafer with its own process and yield curve, and there is no merchant market for finished CoWoS modules. Each denser AI chip needs more HBM stacks, so every new generation places greater, not lesser, load on packaging capacity. Chairman and CEO C.C. Wei said the bottleneck is now capping customer growth and welcomed rival packaging efforts as relief rather than threat, a striking admission from a firm with no equal in the field and little habit of welcoming competition.

What it means for the rest of us

TSMC raised capital spending by as much as $12 billion in a single quarter and locked in a $265 billion Arizona commitment, with new fabs in Taiwan and Japan. The message is blunt: the limit on AI progress is physical silicon and the packaging around it, not software or funding. Labs that have not already secured capacity are competing for a resource whose gap, by management's own account, will not close until well into 2027 or 2028, a timeline that should reset every product roadmap that assumes infinite compute.

For everyone building on top of AI, that means hardware timelines, not model ideas, set the pace. The record quarter is good news for TSMC and its shareholders. For the industry waiting on compute, it is a schedule, and the schedule says the squeeze continues well past the current planning horizon, with consequences that reach from model training to the price of inference. Our Semiconductors section follows the fab build-out, and AI covers what the compute powers.

The geopolitical stakes

The concentration of advanced chipmaking in one company and one island is now a strategic fact that Washington, Tokyo, and Brussels all treat as a vulnerability. The CHIPS Act, the Arizona campus, and the Japan fabs are responses to a single point of failure in the AI supply chain. TSMC's record quarter is good for shareholders, but it also sharpens the question of what happens if that point ever breaks, which is why governments are paying for redundant capacity they would never fund for a normal industry.

That redundancy will be expensive and slow. A fab takes three years to stand up and longer to yield well, so the relief being built today arrives in the late 2020s at best. In the meantime the world runs on one leading-edge source, and every AI roadmap is quietly a bet that source stays available. The record quarter is a vote of confidence in the company, and a reminder of how thin the buffer really is.