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Substrate Shortage, Not Wafers, Is Now the AI Chip Industry's Second Bottleneck

For most of the last four years, the story of the artificial intelligence hardware boom has been told in units of wafers. Foundries were sold out, lithography tools were backordered, and the entire industry strained to…

Semiconductors 1,573 words 8 min read

Substrate Shortage, Not Wafers, Is Now the AI Chip Industry's Second Bottleneck — Semiconductors No Image Semiconductors
Lead image · Filed 30 September 2026, 02:37

Substrate Shortage, Not Wafers, Is Now the AI Chip Industry's Second Bottleneck

Introduction

For most of the last four years, the story of the artificial intelligence hardware boom has been told in units of wafers. Foundries were sold out, lithography tools were backordered, and the entire industry strained to secure enough silicon to satisfy the appetite of data centre operators building out GPU clusters. That crunch has eased at the edges, but a second and less glamorous constraint has moved decisively to the front of the queue.

That constraint is the package substrate. On 29 September 2026, Advanced Substrate Technologies (AST), the Singapore joint venture between Broadcom and Japan's Toppan Holdings, formally opened a 95,000-square-metre manufacturing facility in the Jurong Lake District dedicated to high-end Flip Chip Ball Grid Array substrates. The timing is not coincidental. It reflects a genuine shift in where the binding physical constraint on AI hardware production now sits, and it is why substrate capacity has become the sector's most closely watched number after wafer starts.

What an FC-BGA Substrate Actually Does

It is worth being precise about the component, because "substrate" is used loosely in industry commentary and the confusion drives a lot of the market chatter. An FC-BGA substrate is not a chip. It is a multi-layer printed circuit board, built from glass-reinforced organic laminate, that sits physically between the silicon die and the larger system board.

Its job is deceptively simple and enormously demanding. The die is mounted face-down onto the substrate, and the entire electrical connection surface of the chip — potentially many thousands of contacts — is routed through the substrate's internal copper layers out to a ball grid array on its underside. Those balls solder to the motherboard. Everything the chip communicates, it communicates through that sandwich.

This is why layer count matters so much. As AI accelerators have grown, the number of die-to-package connections has climbed with them. Routing thousands of high-speed lines across a small organic laminate without violating impedance, signal-integrity or yield constraints is a materials science and lithography problem in its own right, entirely separate from the nanoscales of the silicon. A package that takes a leading-edge wafer weeks to fabricate can then sit idle for months because no substrate is available to mount it on.

Broadcom's own semiconductor group president, Charlie Kawwas, described the problem at the AST launch with unusual bluntness: "We were getting wafers, but we were keeping those precious, expensive wafers waiting for substrates." That inversion is the whole story. The expensive input became the stranded one.

The Scale of the Squeeze

The numbers attached to the substrate market are stark. Industry trackers estimate the global FC-BGA market growing at roughly 9.8% annually through 2031, with Asia Pacific the fastest-growing region and servers and data centres the fastest-growing application. Broader advanced packaging forecasts have been revised upward sharply, from approximately USD 55 billion in 2025 to over USD 120 billion by 2031.

Supply is not keeping pace. The commonly cited estimate is an ABF substrate supply gap of around 10% in the second half of 2026, widening to roughly 21% in 2027 and approximately 42% by 2028. Those are not small percentages. They are the difference between a product line shipping and not shipping.

The upstream inputs are even more concentrated than the substrate fabricators themselves. Ajinomoto, the dominant supplier of ABF build-up film, raised prices by roughly 30% from the third quarter of 2026. Nittobo, the near-monopoly supplier of T-glass reinforcement cloth, increased prices by 20% to 30% and extended lead times from eight-to-ten weeks to more than twenty. When two inputs control most of the world's supply of a material and both are raising prices while doubling backlogs, the constraint is structural rather than cyclical.

Intel's chief executive, Lip-Bu Tan, has been unusually public about the same pressure from the buyer's side. Speaking at Splunk's .conf26 conference on 16 September 2026, he said substrate capacity remains tight and described advanced packaging as the industry's future "Holy Grail" — while noting that only four major suppliers dominate the market, two in Japan and two in Taiwan, and that Intel "has to prepay to get their attention." He used the word "prepay" rather than "compete," which is a fairly accurate summary of how allocation works when four suppliers control the critical path.

Why Singapore, and Why Now

AST's Singapore plant is a direct answer to that arithmetic. The facility broke ground in March 2024 and targets the start of high-value manufacturing by late 2026. It has hired more than 200 engineers, technicians and operational staff since construction began, with plans to add more than 330 further roles.

The first products are large-body, high-layer-count FC-BGA substrates for AI computing and networking equipment. AST will initially supply two Broadcom product families: the Tomahawk networking switches and the company's custom AI accelerators. Toppan contributes manufacturing technology transferred from its existing Niigata plant, which remains the group's main production hub — Singapore is a complementary second site, not a replacement, and CEO Yoshiyuki Iida framed the second location explicitly as both growth capacity and business continuity for Toppan's existing Japanese base.

The decision to put R&D on the same site as production is the part most likely to matter over a multi-year horizon. Singapore's Deputy Prime Minister Gan Kim Yong made the argument directly at the opening: bringing R&D and manufacturing together allows engineers to draw on shop-floor experience to refine processes, which over time builds substrate expertise domestically rather than importing it. Singapore's Economic Development Board and JTC Corporation both backed the project.

Singapore is also assembling the surrounding ecosystem. The state unveiled SG Semiconductor as a national branding and coordination initiative earlier in September, a separate but complementary move. Our coverage of that initiative is in Singapore Unveils SG Semiconductor as Dutch Dealings Deepen the Country's Role in the Global Chip Chain, and the parallel UMC wafer expansion on the island — projected at 1.3 million wafers a year on a USD 6.4 billion investment — is covered under Semiconductors. Building substrates, wafers and packaging capacity in the same geography is a coherent strategy, because the binding constraint on output is the slowest stage in the chain, and no amount of wafer capacity helps if packaging is full.

The Larger Contest

AST does not operate in isolation. ASE has raised 2026 advanced packaging quotations by more than 20% and lifted capital expenditure to a record USD 10.5 billion. Samsung Electro-Mechanics announced a KRW 4.27 trillion (roughly USD 3 billion) investment on 28 September 2026 to expand packaging substrate capacity at its Sejong plant. In Japan, Ibiden — a longtime Intel partner and leading FC-BGA substrate maker — plans to convert idle fab space into a dedicated mass-production line for Intel's EMIB-T substrates, a project valued around KRW 2 trillion and reportedly backed by advance payments from Google, Amazon and Intel. Yields for those EMIB substrates are estimated by analyst Jeff Pu to have improved to around 45%, up from 20–25% two quarters earlier.

At the foundry level, TSMC's monthly CoWoS capacity is expected to reach roughly 130,000 wafers by the end of 2026 against end-2024's 35,000, with further doubling projected around 260,000 wafers by end-2028 — yet even that expansion only narrows the supply gap from roughly 20% down to about 10%. The arithmetic is unforgiving: packaging capacity is compounding, and demand is compounding faster.

Set against that backdrop, the AST opening is one data point rather than a turning point. One 95,000-square-metre facility does not close a 21% gap in 2027, let alone a 42% one in 2028. What it does signal is that the industry's largest buyers have stopped treating substrate supply as a procurement problem and started treating it as a strategic one — a reason to own capacity outright, to prepay suppliers, and to sit in a joint venture rather than negotiate on an open market.

Conclusion

The AI hardware story is frequently told as a race for silicon. The past month suggests the binding constraint has moved one step down the process chain, to the organic laminates that route signals off finished dies. Broadcom's wafers waiting on substrates is the image that captures it: the hardest object in the industry, held in inventory, because the cheap-to-make component in the middle is not available.

Singapore's bet is that geographic concentration in substrates, paired with domestic R&D, is worth more than another increment of wafer capacity somewhere else. Whether that bet pays off will be visible in a very specific place — the layer-count and price of substrates available to AI accelerator designers in 2027 and 2028. The supply gap estimates say the shortage deepens before it eases. Investors and system architects should treat advanced packaging capacity, not wafer starts, as the metric to track. For the wider AI infrastructure picture, see our Cloud and Edge coverage, where the same packaging constraint is already showing up in delivery schedules.

Images

Close-up of a green printed circuit board showing dense copper interconnect traces, plated vias and through-hole solder joints

Illustrative: a magnified view of organic substrate interconnect layers — the same build-up structure used in high-layer-count FC-BGA packages. Not the AST facility itself.

Semiconductor wafer probe station with microscope head, positioning stage and measurement rack

Illustrative: wafer probe and test equipment used to characterise packaged devices. Not photographed at the AST site.

References