Rapidus Signs 17 Design Partners for Its 2nm Fab — the Customer Is Still Missing
Introduction
On October 5, 2026, Rapidus Corporation stood in Tokyo and announced something that sounds like a formality and is not. The company — founded in 2022 to single-handedly rebuild a leading-edge logic industry in Japan after three decades of decline — unveiled a framework called the Rapidus Collaborative Open Rapid Ecosystem, or CORE. The first phase of CORE is a roster of seventeen companies designated Design Solution Associates: a bridge layer that will supply design resources and engineering expertise to Rapidus customers.
The list is worth reading slowly. It contains the two firms that between them control the overwhelming majority of commercial electronic design automation: Synopsys and Cadence. It contains Japan's Dai Nippon Printing, TOPPAN and Toshiba Information Systems. It contains five Malaysian design houses and two of India's largest IT services firms. And it contains AION Silicon, MavissDesign, Quest Global Services and a company simply named NSW.
None of those names is a customer. All of them are suppliers. That distinction is the whole story of Rapidus, and it is why an ecosystem announcement is the right thing for Japan's national champion to be doing in October 2026 — and why it is not the same as having a chip to build.
Main Content
The fab is real; the pipeline is the gap
It would be unfair to describe Rapidus as a paper company, because the physical assets are genuinely there. The IIM-1 facility in Bibi, Chitose, on the island of Hokkaido broke ground in September 2023 and completed its cleanroom the following year. ASML delivered a TWINSCAN NXE:3800E in December 2024 — the first mass-production-grade EUV lithography system installed in Japan — and that tool performed its first exposure on April 1, 2025. The pilot line opened the same month.
The process technology itself is derived from IBM's 2nm gate-all-around nanosheet node, licensed under a partnership signed in December 2022. More than 150 Rapidus engineers were dispatched to the Albany NanoTech Complex in New York across 2023 and 2024 to learn the node, with roughly 80 later returning to Hokkaido to transfer and tune it for production. By July 2026 the company said its 2nm gate-all-around prototype had reached its expected electrical characteristics.
The trouble is what comes next. Rapidus's own 2nm Process Design Kit reached early customers in the first quarter of 2026, and the business plan points to production beginning in the second half of fiscal 2027 and scaling to full volume in 2028, with a capacity ramp from roughly 6,000 wafer starts per month to around 25,000 inside the first year. But as detailed in this analysis of Rapidus's fab roadmap, chief executive Atsuyoshi Koike said in February that more than 60 companies were in talks about 2nm capacity and that preliminary price quotations had gone out to roughly ten of them. Not one had signed a volume agreement.
That gap is the reason CORE exists. A foundry's real moat is not the cleanroom. It is the layer above the cleanroom: the calibrated PDK, the certified EDA flows, the IP catalogue, the mask sets, and the thousands of engineers who already know how to target the node. TSMC spent three decades building that layer, and it is the reason a customer can hand a design to Samsung, Intel or TSMC and get a working part. Rapidus has been trying to build a leading-edge fab with no equivalent software-and-services gravity around it, and CORE is an attempt to assemble that gravity by contract.
Why the EDA names matter most
The most consequential entry on the roster is not a Japanese printing company. It is that both Synopsys and Cadence signed on as Design Solution Associates. Both vendors sell to every foundry on earth, so their presence is not an endorsement of Rapidus over anyone else. What their involvement signals is narrower and more useful: that Rapidus is far enough along its process flow for EDA vendors to justify building and certifying flows against it.
Design flows are fab-specific to a degree outsiders underestimate. Timing libraries, placement and routing rules, extraction decks, power-integrity models and DRC signoff decks are all calibrated to a foundry's actual metal stack and design rules. When a new node appears, the EDA vendor has to certify that its tools produce signoff-accurate results for it. That work is expensive and unglamorous, and it is precisely what a customer at the earliest stage of a tapeout needs. Rapidus said in its own announcement that CORE will expand beyond design to cover EDA, IP and other categories, which suggests the seventeen names are a first tranche rather than the final shape.
The rest of the roster reveals what Rapidus thinks it is short of. Dai Nippon Printing, TOPPAN and Toshiba Information Systems bring packaging and substrate capability — which matters because NEDO's approved fiscal 2026 budget for Rapidus funds chiplet and package design and manufacturing technology, and the company has floated panel-level glass-substrate packaging in its longer-term roadmap. Five Malaysian firms and two Indian IT services companies point at the other stated constraint: Rapidus explicitly invoked "a global shortage of cutting-edge semiconductor talent." A roster that reads like a staffing framework is an honest admission that the binding resource is people, not tools.
The clock, and the two-track national bet
The competitive math is unforgiving. TSMC moved its N2 node to volume production in late 2025 and Samsung began first-generation SF2 mass production the same year, which leaves Rapidus roughly two years behind on a node customers can already buy elsewhere with proven yields. Rapidus has said its homegrown 2nm parts could cost around ten times more than Japan's current mainstream devices, a premium that narrows only with volume — and a fab running well below capacity carries the same fixed depreciation as a full one.
The public money is enormous and increasingly structural. A February 2026 round closed at ¥267.6 billion, split ¥100 billion from the government through the Information-technology Promotion Agency and ¥167.6 billion from 32 private companies, making Tokyo the largest single shareholder under a 2025 legal revision that allowed government equity. That followed roughly ¥1 trillion of additional METI support across fiscal 2026 and 2027, and a further ¥150 billion of equity in early June 2026 that took capital and capital reserves to ¥424.95 billion. The state holds largely non-voting shares giving it roughly 11.5 percent formally, but they convert to about 60 percent if performance deteriorates, alongside a golden share carrying veto power over share transfers and technology partnerships. Total lifetime investment is expected to exceed ¥7 trillion, with roughly ¥5 trillion needed just to reach stable 2nm production.
This is the two-track national strategy in miniature. TSMC's JASM venture in Kumamoto, backed by Sony, Denso and Toyota, began mass production in December 2024 on mature 12nm, 16nm, 22nm and 28nm nodes aimed at automotive and industrial parts — shipping, low risk. Rapidus carries nearly all of the program's execution risk and none of its proven output. EE Times Asia noted that the CORE framework is intended to serve customers both in Japan and overseas, which is the right ambition: a fab with only a domestic customer base cannot fill 25,000 wafer starts a month.
Three signals will settle whether the 2027 ramp holds: a named customer with a committed volume order, published evidence that 2nm yields are tracking toward what TSMC and Samsung already run, and confirmation the capacity ramp is actually climbing. CORE improves the odds on the first by making the design path less lonely. It does not supply a customer.
Conclusion
It is easy to read a seventeen-company roster as a packaging exercise, and the cynicism is not unfounded — consortium announcements are cheap and common. But the specific composition argues against dismissing it. Two EDA vendors, three Japanese packaging and substrate incumbents, a spread of Asian design houses and two Indian IT services firms is not a list assembled to fill a slide. It is a map of the actual work between a tapeout and a shipping part.
What CORE does not do is resolve the question that matters. Rapidus has built a leading-edge fab, licensed a real process, and stood up EUV tooling in a country that had none. It has done all of that roughly two years behind the competition, with no committed volume customer, at a cost projection that assumes ¥5 trillion of public and private money, and with the entire national leading-edge program resting on a single building in Hokkaido. A design ecosystem makes the 2027 date more reachable. It does not make the fab full.
Watch for the first named tapeout, not the eighteenth partner.
Images
Illustrative only: a frame from a Creative Commons-licensed video showing a wafer being edge-handled into process equipment in a cleanroom. It is not Rapidus' IIM-1 facility in Hokkaido, and no company logos or site identifiers are visible in the frame.
Illustrative: a genuine SEM cross-section of glass-frit-bonded silicon wafers produced by Bosch, showing the bond-layer structure that wafer bonding research relies on. It is not a Rapidus 2nm sample and carries no gate-all-around features.
Illustrative: the Hokkaido coast near Abuta and Lake Toyako, in the prefecture where Rapidus is building IIM-1. This is a coastal scene — no fab, factory or industrial facility is visible in the image.
References
- Rapidus Corporation, "Rapidus Unveils 'Rapidus CORE', New Global Ecosystem Framework," October 5, 2026 — https://www.rapidus.inc/en/news_topics/information/20261005-2/
- EE Times Asia, "Rapidus Builds Global Design Ecosystem for Advanced Semiconductor Production," October 2026 — https://www.eetasia.com/rapidus-builds-global-design-ecosystem-for-advanced-semiconductor-production/
- Tom's Hardware, "Rapidus fab roadmap examined — first new leading-edge chipmaker in decades has one Hokkaido fab, a 2027 deadline, and 60 potential customers" — https://www.tomshardware.com/tech-industry/semiconductors/rapidus-fab-roadmap-examined
- PR Newswire, full text of the Rapidus CORE release — https://www.prnewswire.com/news-releases/rapidus-unveils-rapidus-core-new-global-ecosystem-framework-supporting-the-development-and-mass-production-of-cutting-edge-semiconductors-302897923.html
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